Sports timing system

Claim 2

A sports timing system comprising: central processor means; a plurality of peripheral devices; a plurality of event sensing means for sensing events relating to competitors' starting times, arrival times or intermediate times; a single two-wire cable connected between said central processor means and said peripheral devices; first means in said central processor means for repeatedly and alternately impressing first and second voltage differentials across the two wires of said cable to thereby transmit clock pulses to said peripheral devices; said peripheral devices including second means responsive to said event sensing means and said clock pulses for modifying the first voltage impressed across said two wires by said first means when an event is sensed; and, said central processor means including means for sensing that a voltage differential impressed across said two conductors by said first means has been modified by said second means.

Claim 3

A sports timing system as set forth in claim 1 for competitions in which several competitors are simultaneously engaged, each in his own track, the peripheral devices associated with each track being coupled to the two-wire cable through a common electronic interface module.

Claim 4

A sports timing system as set forth in claim 2 for swimming competitions, each track comprising a water lane in a swimming pool.

Claim 5

A sports timing system as set forth in claim 2 wherein the interface module includes a comparator and a code generator for each peripheral device whereby the processor means is enabled to communicate separately with each peripheral device.

Claim 6

A sports timing system as claimed in claim 1 for use in timing competitions of the type wherein each competitor has his own track, there being plural event sensing means associated with each track, said system having one of said peripheral devices for each of said sensing means.

Claim 7

A sports timing system as claimed in claim 5 wherein all of the peripheral devices associated with a single track are enclosed within a single module and said second means in a single module comprises: a single counter for counting said control pulses; a code generator, a comparison means, and a gating means corresponding to said event sensing means; said comparison means each comparing the count in said counter with the code generated by one of said code generators, and enabling one of the gating means; said event sensing means being connected to individual ones of said gating means.

Claim 8

A sports timing system comprising: a central processor; a plurality of peripheral devices; a single two-conductor cable connected to said central processor; means in said central processor for generating a sequence of clock pulses; means in said central processor for applying said clock pulses to said cable as a voltage differential between the two conductors of the cable which varies between a first and a second voltage differential during first and second intervals, respectively, of each clock pulse cycle; a plurality of event sensing means for sensing events relating to competitors' starting, arrival or intermediate times, and producing a control signal for each event sensed; a plurality of peripheral devices having: code generator means; counter means for counting said clock pulses; comparison means for comparing the count in said counter means to the code generated by said code generator means and generating a comparison signal when said count is equal to said code; and, gating means responsive to said comparison signal and a said control signal for modifying the voltage differential between said two conductors during said second interval of a single clock pulse cycle to thereby place on said conductors a signal indicating that an event has been sensed.

Claim 9

A sports timing system comprising: a central processor; a plurality of peripheral devices; a single two-conductor cable connected to said central processor; means in said central processor for generating a sequence of clock pulses; means in said central processor for applying said clock pulses to said cable as a voltage differential between the two conductors of the cable which varies between a first and a second voltage differential during first and second intervals, respectively, of each clock pulse cycle; a plurality of event sensing means for sensing events relating to competitors' starting, arrival or intermediate times, and producing a control signal for each event sensed; a plurality of peripheral devices having: code generator means; counter means for counting said clock pulses; comparison means for comparing the count in said counter means to the code generated by said code generator means and generating a comparison signal when said count is equal to said code; and, gating means responsive to said comparison signal and a said control signal for modifying the voltage differential between said two conductors during said second interval of a single clock pulse cycle to thereby place on said conductors a signal indicating that an event has been sensed.

Claim 10

A sports timing system as claimed in claim 7 for use in timing competitions of the type wherein each competitor has his own track, there being plural event sensing means associated with each track and one of said peripheral devices associated with each sensing means, the peripheral devices for a single track being enclosed within a single housing.

Claim 11

A sports timing system as claimed in claim 8 wherein each track is a lane in a swimming pool and said housings are water-tight.

Claim 12

A sports timing system as claimed in claim 7 wherein each said gating means comprises a logical gate and a transistor, said transistor having a collector and emitter connected to respective ones of said two wires and a base connected to said logical gate.

Claim 13

A sports timing system as claimed in claim 7 wherein the code generator means in each peripheral device generates an address code different from the address code generated by any other peripheral device.

Claim 14

A sports timing system as claimed in claim 7 wherein said counter means comprises a single counter shared by a plurality of said peripheral devices.