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US4156154A
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US
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Flip-flop circuit
Assignee: Toshiba Corp
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Filing: 1977-12-08
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Granted: 1979-05-22
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Expires: 1997-12-08
Abstract
Abstract A flip-flop circuit includes first, second, third and fourth NAND gates each with first and second output terminals. The first output terminal of the first NAND gate C and the first output terminal of the third NAND gate are connected to the input terminals of the second and fourth NAND gates, respectively. The first output terminals of the second and fourth NAND gates are connected to the input terminals of the first and third NAND gates, respectively. The second output terminals of the first and second NAND gates are connected to the input terminals of the third and fourth NAND gates, respectively. The second output terminal of the fourth NAND gate is coupled with the input terminal of the first NAND gate. A first diode is inserted between the input terminals of the first and second NAND gates and second diode is inserted between the third and fourth NAND gates. An input signal is applied to the input terminal of the second NAND gate, and an output signal is taken from the second output terminal of the third NAND gate.
Inventors
- 👤 Tetsuya Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:58
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
98 words
In a flip-flop circuit including at least first and second gates, each logical gate having at least two inputs and at least one output, an output of said first logical gate being coupled as one input of said second logical gate, and an output of said second logical gate being coupled as one input of said first logical gate, the improvement comprising a diode connected between another input of said first logical gate and another input of said second logical gate to permit only unidirectional current flow between said another inputs of said first and second logic gates.
Claim 2
Dependent Claim
98 words
In a flip-flop circuit including at least first and second gates, each logical gate having at least two inputs and at least one output, an output of said first logical gate being coupled as one input of said second logical gate, and an output of said second logical gate being coupled as one input of said first logical gate, the improvement comprising a diode connected between another input of said first logical gate and another input of said second logical gate to permit only unidirectional current flow between said another inputs of said first and second logic gates.
Claim 3
Dependent Claim
252 words
A flip-flop circuit including first, second, third and fourth NAND gates, each NAND gate having at least one input terminal and at least two output terminals, and in which: a first diode is connected forwardly from the input terminal of the first NAND gate to the input terminal of the second NAND gate, and a second diode is connected forwardly from the input terminal of the fourth NAND gate to the input terminal of the third NAND gate; the first output terminal of the first NAND gate is connected to the input terminal of the second NAND gate, the first output terminal of the second NAND gate is connected to the input terminal of the first NAND gate, and the second output terminal of the fourth NAND gate is connected to the input terminal of the first NAND gate; the second output terminal of the first NAND gate is connected to the input terminal of the third NAND gate, the second output terminal of the second NAND gate is connected to the input terminal of the fourth NAND gate, the first output terminal of the third NAND gate is connected to the input terminal of the fourth NAND gate, and the first output terminal of the fourth NAND gate is connected to the input terminal of the third NAND gate; and the input terminal of the second NAND gate comprising an input signal receiving means and the second output terminal of the third NAND gate comprising an output of said flip-flop circuit.
Claim 4
Dependent Claim
252 words
A flip-flop circuit including first, second, third and fourth NAND gates, each NAND gate having at least one input terminal and at least two output terminals, and in which: a first diode is connected forwardly from the input terminal of the first NAND gate to the input terminal of the second NAND gate, and a second diode is connected forwardly from the input terminal of the fourth NAND gate to the input terminal of the third NAND gate; the first output terminal of the first NAND gate is connected to the input terminal of the second NAND gate, the first output terminal of the second NAND gate is connected to the input terminal of the first NAND gate, and the second output terminal of the fourth NAND gate is connected to the input terminal of the first NAND gate; the second output terminal of the first NAND gate is connected to the input terminal of the third NAND gate, the second output terminal of the second NAND gate is connected to the input terminal of the fourth NAND gate, the first output terminal of the third NAND gate is connected to the input terminal of the fourth NAND gate, and the first output terminal of the fourth NAND gate is connected to the input terminal of the third NAND gate; and the input terminal of the second NAND gate comprising an input signal receiving means and the second output terminal of the third NAND gate comprising an output of said flip-flop circuit.
Claim 5
Dependent Claim
249 words
A flip-flop circuit having first, second, third and fourth logical gates, each gate being an integrated injection logic circuit and each gate having at least one input terminal and at least two output terminals, and, in which: the first output terminal of the first logical gate is connected to the input terminal of the second logical gate, and the second output terminal of the first logical gate is connected to the input terminal of the third logical gate; the first output terminal of the second logical gate is connected to the input terminal of the first logical gate and to the second output terminal of the fourth logical gate, and the second output terminal of the second logical gate is connected to the input terminal of the fourth logical gate; the first output terminal of the third logical gate is connected to the input of the fourth logical gate; the first output terminal of the fourth logical gate is connected to the input terminal of the third logical gate; a first diode is connected forwardly from the input terminal of the first logical gate to the input terminal of the second logical gate; a second diode is connected forwardly from the input terminal of the fourth logical gate to the input terminal of the third logical gate; and the input terminal of the second logical gate comprising an input signal receiving means and the second output terminal of the third logical gate comprising an output of said flip-flop circuit.
Claim 6
Dependent Claim
249 words
A flip-flop circuit having first, second, third and fourth logical gates, each gate being an integrated injection logic circuit and each gate having at least one input terminal and at least two output terminals, and, in which: the first output terminal of the first logical gate is connected to the input terminal of the second logical gate, and the second output terminal of the first logical gate is connected to the input terminal of the third logical gate; the first output terminal of the second logical gate is connected to the input terminal of the first logical gate and to the second output terminal of the fourth logical gate, and the second output terminal of the second logical gate is connected to the input terminal of the fourth logical gate; the first output terminal of the third logical gate is connected to the input of the fourth logical gate; the first output terminal of the fourth logical gate is connected to the input terminal of the third logical gate; a first diode is connected forwardly from the input terminal of the first logical gate to the input terminal of the second logical gate; a second diode is connected forwardly from the input terminal of the fourth logical gate to the input terminal of the third logical gate; and the input terminal of the second logical gate comprising an input signal receiving means and the second output terminal of the third logical gate comprising an output of said flip-flop circuit.
Claim 7
Dependent Claim
76 words
A flip-flop circuit according to claim 3, in which the first logical gate has a junction area for the collector region of the second output terminal thereof which is larger than that for the collector region of the first output terminal thereof; and the third logical gate has a junction area for the collector region of the second output terminal thereof which is larger than that for the collector region of the first output terminal thereof.
Claim 8
Dependent Claim
40 words
A flip-flop circuit according to claim 3, in which said first logical gate includes a third output terminal connected to said second output terminal; and said third logical gate includes a third output terminal connected to said second output terminal.
Claim 9
Dependent Claim
49 words
A flip-flop circuit according to claim 3, comprising a third diode connected forwardly from the input terminal of the second logical gate to the first output terminal thereof; and a fourth diode connected fowardly from the input terminal of the third logical gate to the first output terminal thereof.
Claim 10
Dependent Claim
76 words
A flip-flop circuit according to claim 6, in which the second logical gate has a junction area for the collector region of the second output terminal thereof which is larger than that for the collector region of the first output terminal thereof; and the fourth logical gate has a junction area for the collector region of the second output terminal thereof which is larger than that for the collector region of the first output terminal thereof.
Claim 11
Dependent Claim
42 words
A flip-flop circuit according to claim 6, in which said second logical gate includes a third output terminal connected to the second output terminal thereof and said fourth logical gate includes a third output terminal connected to the second output terminal thereof.
References Cited (Backward Citations)
US3603815A
Cited
US3930266A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-21 | 1982-11-20 | 1983-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-21 | 1986-11-20 | 1987-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-21 | 1990-11-20 | 1991-05-22 | $7700.00 | Window Closed / Lapsed |