Data bit assembler

Claim 2

In a printer having a plurality of marking means each selectable by a control signal for recording a mark, apparatus for supplying said control signals comprising: data bit assembler means having a plurality of storage cells, each corresponding to a said marking means, said cells being arranged in a matrix of rows and columns and addressable by rows for selective parallel storage of said data bits in the cells within a row, said plurality of cells being activatable for serial readout of data within each said row and said rows being readable in succession; buffer means having a plurality of storage positions for receiving in parallel a plurality of said data bits; buffer readout means connected between said cell columns and said buffer storage positions for applying thereto in parallel a predetermined group of bits in said plurality; means for addressing predetermined rows for successively storing groups of bits appearing at said columns of cells; and means for serially reading out the data bits within a said row and sequentially from said rows as control signals for respective ones of said marking means.

Claim 3

Apparatus as described in claim 1 wherein said data assembler means includes a plurality of shift registers each operable for serial readout of data bits therein.

Claim 4

Apparatus as described in claim 1 wherein each of said rows of cells is addressable with groups of said data bits a plurality of times prior to the reading out of said rows.

Claim 5

Apparatus as described in claim 2 wherein the shift registers in said array are read out concurrently to respective groups of said marking means.

Claim 6

Apparatus as described in claim 4 wherein said marking means includes supplemental storage means for the data bits read out from said shift registers in said array.

Claim 7

Apparatus as described in claim 1 wherein said buffer storage means includes means for shifting said parallel plurality of data bits at least one column with respect to said assembler means.

Claim 8

Apparatus as described in claim 1 wherein said buffer means includes means for shifting bit plurality of data bits a number of stages one less than the number of columns in said assembler means.

Claim 9

An arrangement for printing characters at varying positions comprising: a series of marking means; bit assembler means having a plurality of bit storage cells, each corresponding to a said marking means, said cells being arranged in rows and columns and addressable by rows for parallel storage of successive groups of data bits therein, with each bit position in a said group corresponding to a said column and activatable for serial readout of said storage bits in said columns of cells in a plurality of rows; buffer storage means connected to said bit assembler for receiving in parallel the bits from a byte of character data and including means for serially shifting said byte; control means operable for selectively transferring groups of said bit data from said buffer means to said bit assembler columns; address means operable to select a row of said cells in said bit assembler for storage of a said data group; address incrementing means for changing said address to successive rows of said cells for storing additional groups of bits from said buffer storage means until said data byte has been completely stored; and means for transferring said data bits to said marking means serially from the column positions in a row and from a plurality of said rows.

Claim 10

An arrangement for printing characters at varying positions comprising: a series of marking means; bit assembler means having a plurality of bit storage cells, each corresponding to a said marking means, said cells being arranged in rows and columns and addressable by rows for parallel storage of successive groups of data bits therein, with each bit position in a said group corresponding to a said column and activatable for serial readout of said storage bits in said columns of cells in a plurality of rows; buffer storage means connected to said bit assembler for receiving in parallel the bits from a byte of character data and including means for serially shifting said byte; control means operable for selectively transferring groups of said bit data from said buffer means to said bit assembler columns; address means operable to select a row of said cells in said bit assembler for storage of a said data group; address incrementing means for changing said address to successive rows of said cells for storing additional groups of bits from said buffer storage means until said data byte has been completely stored; and means for transferring said data bits to said marking means serially from the column positions in a row and from a plurality of said rows.

Claim 11

Apparatus as described in claim 8 wherein said buffer storage means includes means for shifting said data byte a number of positions one less than the number of columns in said bit assembler.

Claim 12

Apparatus as described in claim 8 wherein said address incrementing means is operable to increment said address a number of times equal to the number of groups of data in said data byte.

Claim 13

Apparatus as described in claim 8 wherein said bit assembler includes a matrix of binary storage cells, each settable from a reset state to a set state only when data is present for storage irrespective of the number of times said cells are addressed.