US4151373A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transmission system
Assignee: OMNISEC AG TROCKENLOOSTRASSE 91 CH-8105 REGENSDORF SWITZERLAND A Co OF SWITZERLAND
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Filing: 1977-09-07
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Granted: 1979-04-24
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Expires: 1997-09-07
Abstract
Abstract A system for inserting extra-information bits into a bit sequence to be transmitted over a transmission channel and for suppressing such bits from the transmitted bit sequence, the system having an inserter at the transmitting end and a suppressor at the receiving end, the inserter converting an input bit sequence which it receives at a first repetition frequency into a second repetition frequency which is higher to correspond to the inserted extra bits, by the insertion of m extra bits per m.k.n bits of the input bit sequence k, n and m denoting integers which are greater than zero, the suppressor restoring the original input bit sequence at the first repetition frequency and the extra-information bits from the output bit sequence which it receives from the transmitter at the second repetition frequency, the inserter comprising a first repetition frequency generator which derives the output bit sequence repetition frequency from the input sequence repetition frequency and complies with the condition n.k≧ 50.
Inventors
- 👤 Walter R. Widmer
- 👤 Hans-Jorg Klemenz
- 👤 Pierre Schmid
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:04
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/12; H04J3/06; H04J3/0602
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
452 words
A system for inserting extra-information bits into a bit sequence to be transmitted over a transmission channel and for suppressing such bits from the transmitted bit sequence, the system including at the transmitting end an inserter which inserts into an input bit sequence arriving at a first clock frequency m extra bits per m.k.n bits of the input bit sequence to produce an output bit sequence having a second clock frequency which is higher than the first clock frequency by the number of inserted extra bits, k, n and m denoting integers which are greater than zero, and further including at the receiving end a suppressor which filters out said inserted extra bits from the output bit sequence and thereby restores the original input frequency at the first clock frequency, said inserter comprising: first clock generating means deriving from said input bit sequence at said first clock frequency a clock signal having a second clock frequency; a first intermediate store; first means for writing the input sequence thereinto at the first clock frequency and for reading out such sequence at the second clock frequency; first fillig monitors for the first intermediate store; a source for extra-information bits; a source for a sync bit sequence; a first selector for selectively connecting the first intermediate store, the source for extra-information bits, and the source for a sync bit sequence to the transmission channel; a first controller which controls the first selector in dependence on the first filling monitors; and a first coding stage connected to the first controller and controlling, according to a given coding program, aperiodically the number of extra-information bits to be inserted into the input bit sequence per insertion operation; and said suppressor comprising: second clock generating means deriving from said output bit sequence at said second clock frequency a clock signal having said first clock frequency; a second intermediate store; second means for writing the transmission end output bit sequence into such store at the second clock frequency and for reading such bit sequence out of the store at the first clock frequency; second filling monitors for the second intermediate store; a sink for extra-information bits; a second selector for selectively connecting the transmission channel to the input of the second intermediate store and the sink; a second controller which controls the second selector in dependence on the second fillng monitors; a sync bit sequence identifier which, when it identifies such a bit sequence, brings the second controller into the stand-by state, and a second coding stage connected to the second controller and controlling, according to said given coding program, the number of extra-information bits which must be suppressed from the output bit sequence to restore the input bit sequence.
Claim 2
Independent Claim
452 words
A system for inserting extra-information bits into a bit sequence to be transmitted over a transmission channel and for suppressing such bits from the transmitted bit sequence, the system including at the transmitting end an inserter which inserts into an input bit sequence arriving at a first clock frequency m extra bits per m.k.n bits of the input bit sequence to produce an output bit sequence having a second clock frequency which is higher than the first clock frequency by the number of inserted extra bits, k, n and m denoting integers which are greater than zero, and further including at the receiving end a suppressor which filters out said inserted extra bits from the output bit sequence and thereby restores the original input frequency at the first clock frequency, said inserter comprising: first clock generating means deriving from said input bit sequence at said first clock frequency a clock signal having a second clock frequency; a first intermediate store; first means for writing the input sequence thereinto at the first clock frequency and for reading out such sequence at the second clock frequency; first fillig monitors for the first intermediate store; a source for extra-information bits; a source for a sync bit sequence; a first selector for selectively connecting the first intermediate store, the source for extra-information bits, and the source for a sync bit sequence to the transmission channel; a first controller which controls the first selector in dependence on the first filling monitors; and a first coding stage connected to the first controller and controlling, according to a given coding program, aperiodically the number of extra-information bits to be inserted into the input bit sequence per insertion operation; and said suppressor comprising: second clock generating means deriving from said output bit sequence at said second clock frequency a clock signal having said first clock frequency; a second intermediate store; second means for writing the transmission end output bit sequence into such store at the second clock frequency and for reading such bit sequence out of the store at the first clock frequency; second filling monitors for the second intermediate store; a sink for extra-information bits; a second selector for selectively connecting the transmission channel to the input of the second intermediate store and the sink; a second controller which controls the second selector in dependence on the second fillng monitors; a sync bit sequence identifier which, when it identifies such a bit sequence, brings the second controller into the stand-by state, and a second coding stage connected to the second controller and controlling, according to said given coding program, the number of extra-information bits which must be suppressed from the output bit sequence to restore the input bit sequence.
Claim 3
Dependent Claim
13 words
The system of claim 1 wherein the product n.k is at least 50.
Claim 4
Dependent Claim
15 words
The system of claim 2 wherein the product n.k is at least 10 3 .
Claim 5
Dependent Claim
92 words
The system according to claim 1 wherein the first clock generating means produce from the first clock frequency: periodically, a first pulse group series which comprises n consecutive groups each containing k bits and in which adjacent pulse groups are phaseshifted relatively to one another by the n th part of the pulse period of the last-mentioned clock frequency; and, after each n th group of bits each, an additional pulse, the first pulse group series together with the additional pulses constituting said second clock frequency of the transmitting-end output bit sequence.
Claim 6
Dependent Claim
88 words
The system according to claim 4 wherein the second clock generating means produce periodically from the second clock frequency a second pulse group series which comprises n consecutive groups of k bits each and in which adjacent pulse groups are phase-shifted relatively to one another by the n th part of the pulse period of the second clock frequency, and suppressing one pulse after every n th group of the k bits each, the secondpulse group series constituting said first clock frequency of the transmission-end input bit sequence.
Claim 7
Dependent Claim
13 words
The system according to claim 4 wherein n is from 8 to 32.
Claim 8
Dependent Claim
16 words
The system according to claim 4 wherein k is from 2 4 to 2 15 .
Claim 9
Dependent Claim
119 words
The system according to claim 5 wherein the first and second clock frequency generating means each comprise: a phase control circuit controlled by the clock frequency of the respective bit sequence (input or output bit sequence) and a first backwards or forwards counter; a second counter incremented by the clock frequency of the respective input or output bit sequence; a comparator comparing the contents of the two counters and outputting a signal in the event of coincidence; and a pulse generator actuated by the comparator, the pulse generator adjusting itself to the clock frequency of the predetermined minimum number of equally spaced consecutive input signals and producing at its output a constant pulse sequence generated from the last-mentioned frequency.
Claim 10
Dependent Claim
159 words
The system according to claim 5 wherein the first and second clock frequency generating means each comprise: a phase control circuit controlled by the clock frequency of the respective bit sequence and a first backwards or forwards counter a second counter incremented by the clock frequency of the respective input or output bit sequence; a pulse generator; a third counter which is connected to the output of the second counter and which transmits a pulse to the pulse generator at the end of its counting cycle; and a comparator which compares the contents of the first and third counter and in the event of their coincidence outputs a signal to the pulse generator; and the pulse generator of the first clock frequency generating means generates an output pulse from each input pulse - and the pulse generator of the second clock frequency generating means generates an output pulse - only in the absence of signal from the third counter.
Claim 11
Dependent Claim
155 words
The system according to claim 1 wherein the first controller brings the first selector into a position in which the same connects the extra-information bits source to the transmission channel when the first filling monitors indicate the "empty" state of the first intermediate store; the first coding stage produces first break-off signals; and in the presence of such a signal the first controller brings the first selector into a position in which the same connects the first intermediate store to the transmission channel; and the second controller brings the second selector into a position in which the same connects the transmission channel to the extra-information bitssink when the second filling monitors detect the "full" state; the second coding stage produces a second break-off signals, and in the presence of such a signal the second controller brings the second selector into a position in which the same connects the transmission channel to the second intermediate store.
References Cited (Backward Citations)
US4025720A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-23 | 1982-10-23 | 1983-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-23 | 1986-10-23 | 1987-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-23 | 1990-10-23 | 1991-04-24 | $7700.00 | Window Closed / Lapsed |