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US4150337A
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Comparator circuit apparatus
Assignee: Boeing North American Inc
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Filing: 1977-11-21
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Granted: 1979-04-17
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Expires: 1997-11-21
Abstract
Abstract The method and circuitry for detecting two different binary numbers or digital words in a register or counter using logic gates wherein bits are detected using n-1 logic gates when all the digits of each of words or numbers are at the same one of a plurality of possible logic levels. In other words, two numbers such as all logic ones as the first number and all logic zeros as the second number. Specifically, this concept is applied to checking an up-down counter output so that it is prevented from overflowing or underflowing by stopping it at either a count of all logic zeros or all logic ones.
Inventors
- 👤 Daniel R. Sheller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:53
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
56 words
The method of ascertaining that all N of the digits of a binary number have the same logic value in N-1 comparisons comprising the steps of: comparing the logic value of each of the digits with the logic value of at least one other digit, and providing an output signal when all the comparisons are identical.
Claim 2
Independent Claim
56 words
The method of ascertaining that all N of the digits of a binary number have the same logic value in N-1 comparisons comprising the steps of: comparing the logic value of each of the digits with the logic value of at least one other digit, and providing an output signal when all the comparisons are identical.
Claim 3
Independent Claim
82 words
The method of stopping a binary digital counter when all N monitored digits thereof are at the same one of a plurality of possible logic levels wherein the counter has a count input means comprising, the steps of: comparing the logic value of each of the monitored output digits with at least one other output digit in the group of monitored digits in N-1 comparisons, and preventing the application of further count input signals to the counter when all comparisons are identical.
Claim 4
Independent Claim
82 words
The method of stopping a binary digital counter when all N monitored digits thereof are at the same one of a plurality of possible logic levels wherein the counter has a count input means comprising, the steps of: comparing the logic value of each of the monitored output digits with at least one other output digit in the group of monitored digits in N-1 comparisons, and preventing the application of further count input signals to the counter when all comparisons are identical.
Claim 5
Dependent Claim
145 words
Apparatus for preventing counter overflow and underflow comprising, in combination: binary counter means having an overflow count comprising a plurality N of logic 1's and an underflow count having the same plurality N of logic 0's, said counter means including count signal input means; comparison means including N-1 pairs of comparison inputs and means for providing an output signal when each of the N-1 comparison pairs indicate the same comparison result; means connecting the output of said counter means to the comparison means whereby each of the N digit outputs of said counter means are compared with at least one other digit in the N-1 comparisons of said comparison means, and signal supplying means connected to said counter means and to said comparison means for providing an input signal to be counted at times when an output signal is not received from said comparison means.
Claim 6
Dependent Claim
145 words
Apparatus for preventing counter overflow and underflow comprising, in combination: binary counter means having an overflow count comprising a plurality N of logic 1's and an underflow count having the same plurality N of logic 0's, said counter means including count signal input means; comparison means including N-1 pairs of comparison inputs and means for providing an output signal when each of the N-1 comparison pairs indicate the same comparison result; means connecting the output of said counter means to the comparison means whereby each of the N digit outputs of said counter means are compared with at least one other digit in the N-1 comparisons of said comparison means, and signal supplying means connected to said counter means and to said comparison means for providing an input signal to be counted at times when an output signal is not received from said comparison means.
Claim 7
Dependent Claim
153 words
Apparatus for monitoring circuitry containing a digital word to provide an output when N digits thereof are all at the same one of a plurality of possible logic levels comprising, in combination: source means for providing a plurality of parallel lines, a signal on each of which is capable of changing between at least two logic levels; N-1 first logic gate means, each connected to two of said plurality of lines such that the signal logic level of each of said plurality of lines is compared to that of another line, each of said gate means providing a given logic level output at output means thereof when the input signal logic levels are identical, and second logic gate means connected to the output means of all of said N-1 first gate means for receiving input signals therefrom and for providing an output control signal when all inputs are of said given logic level.
Claim 8
Dependent Claim
153 words
Apparatus for monitoring circuitry containing a digital word to provide an output when N digits thereof are all at the same one of a plurality of possible logic levels comprising, in combination: source means for providing a plurality of parallel lines, a signal on each of which is capable of changing between at least two logic levels; N-1 first logic gate means, each connected to two of said plurality of lines such that the signal logic level of each of said plurality of lines is compared to that of another line, each of said gate means providing a given logic level output at output means thereof when the input signal logic levels are identical, and second logic gate means connected to the output means of all of said N-1 first gate means for receiving input signals therefrom and for providing an output control signal when all inputs are of said given logic level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-16 | 1982-10-16 | 1983-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-16 | 1986-10-16 | 1987-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-16 | 1990-10-16 | 1991-04-17 | $7700.00 | Window Closed / Lapsed |