Digital multiplexer incorporating high-speed analog sampling gates

Claim 1

In a digital data-processing system including a multiplicity of sources of binary pulse trains of like frequency and coincident pulse periods, and a multiplexer operable to sample said binary pulse trains in cyclic succession and to synthesize a composite pulse train from the resulting samples, the improvement wherein said multiplexer comprises: a plurality of sampling gates each consisting of at least six diodes defining a plurality of four-arm bridge circuits with two adjoining arms in common, each of said bridge circuits having a pair of noncommon arms interconnected at a first junction, said common arms being interconnected at a second junction, said common and noncommon arms being interconnected at third and fourth junctions, each of said sources being connected to the first junction of a respective bridge circuit, the second junctions of all sampling gates being connected to a common output terminal; and a supply of switching voltages connected across the third and fourth junctions of each sampling gate for successively unblocking said sampling gates at staggered intervals in the course of a pulse period, thereby producing on said output terminal a multi-level pulse train with pulse amplitudes proportional to the algebraic sums of binary voltages concurrently present on the first junctions of any of said sampling gates.