Patent US4149301A successfully refreshed from Google Patents.
US4149301A
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Monolithic semiconductor integrated circuit-ferroelectric memory drive
Assignee: Ferrosil Corp
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Filing: 1978-02-13
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Granted: 1979-04-17
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Expires: 1998-02-13
Abstract
Abstract A monolithic semiconductor integrated circuit - ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 5,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
Inventors
- 👤 Robert C. Cook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:58
CPC Classifications
H; H10; H10B; H10B53/00; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435; Y10T29/49; Y10T29/49002; Y10T29/4902; Y10T29/49069; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49146
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
113 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein; c. depositing a conductive layer and forming a bottom electrode; D. applying a ferroelectric layer; E. filling any imperfections in said ferroelectric layer with insulative material; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and G. applying conductive material to the bonding and interconnect pads.
Claim 2
Independent Claim
113 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein; c. depositing a conductive layer and forming a bottom electrode; D. applying a ferroelectric layer; E. filling any imperfections in said ferroelectric layer with insulative material; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and G. applying conductive material to the bonding and interconnect pads.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnections are composed of doped polysilicon.
Claim 5
Dependent Claim
24 words
The method of claim 1 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitride and sputtered dielectrics.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnections are composed of a metal.
Claim 7
Dependent Claim
27 words
The method of claim 1 wherein said top and bottom electrodes are metals or metal alloys which are applied by reactive sputtering in the pressence of oxygen.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein said ferroelectric KNO 3 layer has a thickness less than 110 microns.
Claim 9
Dependent Claim
26 words
The method of claim 1 wherein said ferroelectric KNO 3 layer has a thickness within a range of from 100 Angstrom units to 5,000 Angstrom units.
Claim 10
Dependent Claim
33 words
The method of claim 1 wherein said ferroelectric potassium nitrate layer has a thickness of less than 1 micron and comprises Phase III potassium nitrate which is stable at standard temperature and pressure.
Claim 11
Dependent Claim
36 words
The method of claim 9 wherein said first layer interconnections are composed of materials selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive metal oxides.
Claim 12
Dependent Claim
33 words
The method of claim 1 wherein the top electrode is formed by defining the top conductive layer by standard photoresist techniques and back sputtering said metal layer until the top electrode is defined.
Claim 13
Dependent Claim
19 words
The method of claim 11 wherein the top conductive layer is partially etched before subjecting it to back sputtering.
Claim 14
Independent Claim
87 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; and G. applying conductive material to the bonding and interconnect pads.
Claim 15
Independent Claim
87 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; and G. applying conductive material to the bonding and interconnect pads.
Claim 16
Dependent Claim
15 words
The method of claim 13 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 17
Dependent Claim
15 words
The method of claim 13 wherein said first layer interconnections are composed of doped polysilicon.
Claim 18
Dependent Claim
24 words
The method of claim 13 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitride and sputtered dielectrics.
Claim 19
Dependent Claim
15 words
The method of claim 13 wherein said first layer interconnections are composed of a metal.
Claim 20
Independent Claim
118 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; G. depositing a conductive layer and forming a top electrode; H. depositing a top non-semiconductor dielectric layer uniformly; I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and J. applying conductive material to the bonding and interconnect pads.
Claim 21
Independent Claim
118 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; G. depositing a conductive layer and forming a top electrode; H. depositing a top non-semiconductor dielectric layer uniformly; I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and J. applying conductive material to the bonding and interconnect pads.
Claim 22
Dependent Claim
15 words
The method of claim 18 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 23
Dependent Claim
15 words
The method of claim 18 wherein said first layer interconnections are composed of doped polysilicon.
Claim 24
Dependent Claim
24 words
The method of claim 18 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitrate and sputtered dielectrics.
Claim 25
Dependent Claim
15 words
The method of claim 18 wherein said first layer interconnections are composed of a metal.
Claim 26
Independent Claim
76 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad via therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides;
Claim 27
Independent Claim
76 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad via therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides;
Claim 28
Dependent Claim
52 words
D. applying a ferroelectric layer; E. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and F. applying conductive material to the bonding and interconnect pads.
Claim 29
Dependent Claim
52 words
D. applying a ferroelectric layer; E. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and F. applying conductive material to the bonding and interconnect pads.
Claim 30
Dependent Claim
15 words
The method of claim 23 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 31
Dependent Claim
15 words
The method of claim 23 wherein said first layer interconnections are composed of doped polysilicon.
Claim 32
Dependent Claim
24 words
The method of claim 23 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitride and sputtered dielectrics.
Claim 33
Dependent Claim
15 words
The method of claim 23 wherein said first layer interconnections are composed of a metal.
Claim 34
Dependent Claim
27 words
The method of claim 23 wherein said top and bottom electrodes comprise conductive materials selected from the group consisting of indium-tin oxide, tin oxide and palladium oxide.
Claim 35
Dependent Claim
21 words
The method of claim 23 wherein said top and bottom electrodes are conductive metal oxides which are applied by RF sputtering.
Claim 36
Dependent Claim
27 words
The method of claim 23 wherein said top and bottom electrodes and metals or metal alloys which are applied by reactive sputtering in the presence of oxygen.
Claim 37
Dependent Claim
36 words
The method of claim 23 wherein said first layer interconnections are composed of materials selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive metal oxides.
Claim 38
Dependent Claim
18 words
The method of claim 23 wherein said ferroelectric KNO 3 layer has a thickness less than 110 microns.
Claim 39
Dependent Claim
26 words
The method of claim 23 wherein said ferroelectric KNO 3 layer has a thickness within a range of from 100 Angstrom units to 5,000 Angstrom units.
Claim 40
Dependent Claim
33 words
The method of claim 22 wherein said ferroelectric potassium nitrate layer has a thickness of less than 1 micron and comprises Phase III potassium nitrate which is stable at standard temperature and pressure.
Claim 41
Dependent Claim
33 words
The method of claim 23 wherein the top electrode is formed by defining the top conductive layer by standard photo-resist techniques and back sputtering said metal layer until the top electrode is defined.
Claim 42
Dependent Claim
19 words
The method of claim 35 wherein the top conductive layer is partially etched before subjecting it to back sputtering.
Claim 43
Independent Claim
138 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and G. applying conductive material to the bonding and interconnect pads.
Claim 44
Independent Claim
138 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; and G. applying conductive material to the bonding and interconnect pads.
Claim 45
Dependent Claim
15 words
The method of claim 37 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 46
Dependent Claim
15 words
The method of claim 37 wherein said first layer interconnections are composed of doped polysilicon.
Claim 47
Dependent Claim
24 words
The method of claim 37 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitride and sputtered dielectrics.
Claim 48
Dependent Claim
15 words
The method of claim 37 wherein said first layer interconnections are composed of a metal.
Claim 49
Dependent Claim
27 words
The method of claim 37 wherein said top and bottom electrodes comprise conductive materials selected from the group consisting of indium-tin oxide, tin oxide and palladium oxide.
Claim 50
Dependent Claim
21 words
The method of claim 37 wherein said top and bottom electrodes are conductive metal oxides which are applied by RF sputtering.
Claim 51
Dependent Claim
27 words
The method of claim 37 wherein said top and bottom electrodes are metals or metal alloys which are applied by reactive sputtering in the presence of oxygen.
Claim 52
Dependent Claim
36 words
The method of claim 37 wherein said first layer interconnections are composed of materials selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive metal oxides.
Claim 53
Independent Claim
159 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; G. depositing a top non-semiconductor dielectric layer uniformly; H. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and I. applying conductive material to the bonding and interconnect pads.
Claim 54
Independent Claim
159 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. depositing a conductive layer and forming a top electrode wherein said conductive layer is selected from the group consisting essentially of conductive metal oxides, metals and metal alloys which will oxidize to form conductive oxides; G. depositing a top non-semiconductor dielectric layer uniformly; H. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and I. applying conductive material to the bonding and interconnect pads.
Claim 55
Dependent Claim
15 words
The method of claim 46 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 56
Dependent Claim
15 words
The method of claim 46 wherein said first layer interconnections are composed of doped polysilicon.
Claim 57
Dependent Claim
24 words
The method of claim 46 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitrate and sputtered dielectrics.
Claim 58
Dependent Claim
15 words
The method of claim 46 wherein said first layer interconnections are composed of a metal.
Claim 59
Dependent Claim
27 words
The method of claim 46 wherein said top and bottom electrodes comprise conductive materials selected from the group consisting of indium-tin oxide, tin oxide and palladium oxide.
Claim 60
Dependent Claim
21 words
The method of claim 46 wherein said top and bottom electrodes and conductive metal oxides which are applied by RF sputtering.
Claim 61
Dependent Claim
27 words
The method of claim 46 wherein said top and bottom electrodes are metals or metal alloys which are applied by reactive sputtering in the presence of oxygen.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1982-04-16 | 1982-10-16 | 1983-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-16 | 1986-10-16 | 1987-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-16 | 1990-10-16 | 1991-04-17 | $7700.00 | Window Closed / Lapsed |