US4147941A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time displaced signal sorting apparatus
Assignee: RCA Corp
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Filing: 1977-12-07
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Granted: 1979-04-03
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Expires: 1997-12-07
Abstract
Abstract A circuit is receptive of two time-spaced input signals at two respective input terminals, where either terminal may receive the first arriving input signal, for producing at first and second output terminals, signals indicative respectively of the time of arrival of the first and second input signals.
Inventors
- 👤 Walter R. Curtice
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:37
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A circuit for providing a relatively early signal pulse and a relatively late signal pulse at first and second output terminals, respectively, corresponding in time to first arriving and second arriving input signal pulses, each signal being applied to a different one of a pair of input terminals of said circuit, the first pulse being present when the second pulse arrives, comprising: means responsive to said input pulses for producing, as a function of time, a sum signal pulse having an amplitude directly related to the sum of the respective amplitudes of said output pulses; means coupled to said summing means for producing at said first output terminal said relatively early pulse in response to the leading edge of said sum pulse; and means coupled to said summing means for producing at said second output terminal said relatively late pulse in response to the amplitude of said sum signal exceeding a known amplitude greater than the amplitude of the first arriving input pulse.
Claim 2
Dependent Claim
163 words
A circuit for providing a relatively early signal pulse and a relatively late signal pulse at first and second output terminals, respectively, corresponding in time to first arriving and second arriving input signal pulses, each signal being applied to a different one of a pair of input terminals of said circuit, the first pulse being present when the second pulse arrives, comprising: means responsive to said input pulses for producing, as a function of time, a sum signal pulse having an amplitude directly related to the sum of the respective amplitudes of said output pulses; means coupled to said summing means for producing at said first output terminal said relatively early pulse in response to the leading edge of said sum pulse; and means coupled to said summing means for producing at said second output terminal said relatively late pulse in response to the amplitude of said sum signal exceeding a known amplitude greater than the amplitude of the first arriving input pulse.
Claim 3
Dependent Claim
20 words
The combination as set forth in claim 1 wherein said means producing said early pulse comprises a pulse shaping circuit.
Claim 4
Dependent Claim
18 words
The combination as set forth in claim 2 wherein said pulse shaping circuit comprises a step recovery diode.
Claim 5
Dependent Claim
58 words
The combination as set forth in claim 1 wherein said means producing said late pulse comprises threshold means responsive to said sum signal for producing a signal corresponding in time to the initial concurrent presence of both input signals at said summing means and further comprises means responsive to said threshold means signal for producing said late pulse.
Claim 6
Dependent Claim
22 words
The combination as set forth in claim 4 wherein said means responsive to said threshold means signal comprises a pulse shaping circuit.
Claim 7
Dependent Claim
18 words
The combination as set forth in claim 5 wherein said pulse shaping cricuit comprises a step recovery diode.
Claim 8
Dependent Claim
17 words
The combination as set forth in claim 4 wherein said threshold means comprises a reverse biased diode.
Claim 9
Dependent Claim
18 words
The combination as set forth in claim 7 wherein said reverse biased diode is a Schottky barrier diode.
Claim 10
Dependent Claim
18 words
The combination as set forth in claim 1 wherein said summing means comprises a dual gate transistor circuit.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-02 | 1982-10-02 | 1983-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-02 | 1986-10-02 | 1987-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-02 | 1990-10-02 | 1991-04-03 | $7700.00 | Window Closed / Lapsed |