Testing the differential response times of a plurality of circuits

Claim 5

The method of claim 2, wherein the circuits are multiple gate functions integrated on a single chip of semiconductor material, the method further comprising: generating the reference signal by passing the output signals of all the gate functions through an OR gate which generates the reference signal when it receives the first output signal; determining the slowest propagation delay of the gate functions by passing the output signals of all of the gate functions through an AND gate which gives an output signal when it receives all of the gate function output signals; and comparing the delayed reference signal of the OR gate and the output signal of the AND gate in a comparator circuit which changes states if the delayed reference signal of the OR gate arrives before the output signal of the AND gate.

Claim 6

The method of claim 2, wherein the circuits are multiple gate functions integrated on a single chip of semiconductor material, the method further comprising: generating the reference signal by passing all of the output signals of the gate functions to a NAND gate which generates the reference signal when it receives the first gate function output signal; and comparing each of the gate function output signals individually to the delayed reference signal of the NAND gate to determine which individual gate functions have a propagation delay time greater than the delayed reference signal.

Claim 7

The method of claim 2, wherein the circuits are multilple gate functions integrated on a single chip of semiconductor material and each of the gate functions has a low state and a high state, the method further comprising: generating a first reference signal indicative of the fastest propagation delay time for the gate functions passing from a low state to a high state by coupling the outputs of the gate functions to a NAND gate which generates the first reference signal when it receives the first gate function output signal passing from a low state to a high state; generating a second reference signal indicative of the fastest propagation delay time for the gate functions passing from a high state to a low state by coupling the outputs of the gate functions to a second NAND gate which generates the second reference signal when it receives the first gate function output signal passing from a high state to a low state; delaying the first and second reference signals by a time equal to the maximum allowable time difference between the gate functions with the fastest propagation delay time and the slowest propagation delay time; comparing each of the individual gate function output signals with the delayed first reference signal of the first NAND gate to determine which gate functions have a propagation delay time for passing from the low state to the high state greater than the delayed first reference signal; and comparing each of the individual gate function output signals with the delayed second reference signal of the NAND gate to determine which gate functions have a propagation delay time for passing from the high state to the low state greater than the delayed second reference signal.

Claim 8

The method of claim 2, further comprising: comparing the propagation delay times of each of the circuits individually to a reference propagation delay time prior to comparing the circuits to the delayed reference signal; and identifying if any of the circuits have a propagation delay time which exceeds the reference maximum propagation delay time.

Claim 13

The apparatus of claim 8, wherein the circuits are multiple gate functions integrated on a single chip of semiconductor material, the apparatus further comprising: an OR gate coupled to the output signals of each of the gate functions to generate the reference signal when it receives the first gate function output signal thereby establishing the fastest propagation delay time; an AND gate coupled to the output signals of each of the gate functions to give an output signal only when it receives all of the gate function output signals, thereby establishing the slowest propagation delay time; and means for comparing the delayed reference signal of the OR gate and the output signal of the AND gate.

Claim 14

The apparatus of claim 9, wherein the comparing means is a bistable circuit which will only change states if the delayed reference signal of the OR gate arrives before the output signal of the AND gate.

Claim 15

The apparatus of claim 8, wherein the circuits are multiple gate functions integrated on a single chip of semiconductor material, the apparatus further comprising: a NAND gate coupled to the output signals of the gate functions to generate the reference signal when it receives the first gate function output signal thereby determining the fastest propagation delay time; and means for comparing each of the gate function output signals individually to the delayed reference signal of the NAND gate to determine which individual gate functions have a propagation delay time greater than the delayed reference signal.

Claim 16

The apparatus of claim 8, wherein the circuits are multiple gate functions integrated on a single chip of semiconductor material and each of the gate functions has a low state and a high state, the apparatus further comprising: a first NAND gate coupled to the output signals of the gate functions to generate a first reference signal when it receives the first gate function output signal passing from a low state to a high state thereby determining the fastest propagation delay time of the gate functions for passing from a low state to a high state; a second NAND gate coupled to the output signals of the gate functions to generate a second reference signal when it receives the first gate function output signal passing from a high state to a low state thereby determining the fastest propagation delay time of the gate functions for passing from a high state to a low state; means for adding a delay time to the first and second reference signals equal to the maximum allowable time difference between the circuits with the fastest propagation delay time and the shortest propagation delay time; means for comparing each of the individual gate function output signals with the delayed first reference signal of the first NAND gate to determine which gate functions have a propagation delay time for passing from the low state to the high state greater than the delayed first reference signal; and means for comparing each of the individual gate function output signals with the delayed second reference signal of the second NAND gate to determine which gate functions have a propagation delay time for passing from the high state to the low state greater than the delayed second reference signal.

Claim 17

The apparatus of claim 8, further comprising: means for comparing the propagation delay times of each of the circuits individually to a reference maximum propagation delay time prior to comparing the circuits to the delayed reference signal; and means for indicating whether any of the circuits has a propagation delay time greater than the reference maximum propagation delay time.