US4145747A
Expired / Lapsed
US
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Method for establishing a tap coefficient of an adaptive automatic equalizer
Assignee: KDDI Corp
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Filing: 1977-09-15
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Granted: 1979-03-20
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Expires: 1997-09-15
Abstract
Abstract A method and apparatus is provided for adjusting the tap coefficient of an adaptive automatic equalizer having a plurality of tap registers. An input signal is repetitively applied to a train of tapped delay elements and the sum of the weighted output of each tap output is obtained. An error output is obtained by taking the difference between the sum of the weighted output of each tap output and a reference signal, and a correlation value is obtained between the error output and each tap output of the delay elements. The improvement comprises storing the tap weights of each of the tapped registers and obtaining the total sum of each tap weight of one of the registers wherein the tap weight of a tap is the correlation value. This step is repeated M times, where M is an integer so that the total sum of each tap weight in another of the tapped registers is obtained and the error output is added to the total sum, determining a value of tap coefficient by the final total sum after M adjustments of the most rapid equalization. The optimum coefficient is obtained by using the value of the tap coefficient for the most rapid equalization of the tapped registers and the weight of the taps of the delay element is revised by the optimum coefficient-weight-sum of the contents of the tapped register and the tapped delay elements, thereby adjusting the weight of each tap of the delay elements.
Inventors
- 👤 Hiroshi Sakaki
- 👤 Sotokichi Shintani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:50
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
232 words
In a method for adjusting the tap coefficient of an adaptive automatic equalizer having a plurality of tapped registers comprising the steps of: applying an input signal repetitively to a train of tapped delay elements; obtaining a sum of the weighted output of each tap output; obtaining an error output by taking the difference between the sum of the weighted output of each tap output and a reference signal; and obtaining a correlation value between said error output and each tap output of said delay elements; the improvement comprising: storing the tap weights of each of said tapped registers; obtaining the total sum of each tap weight of one of said tapped registers wherein the weight of a tap is said correlation value; repeating M times, where M is an integer, the obtaining the total sum of each tap weight in another of said tapped registers; adding said error output to said total sum; determining the value of a tap coefficient by the final total sum after M adjustments for the most rapid equalization; obtaining the optimum coefficient using said value of said top coefficient for the most rapid equalization of said tapped registers; and revising the weight of the taps of said delay elements by the optimum coefficient-weight-sum of the contents of said tapped register and said tapped delay elements, thereby adjusting the weight of each tap of said delay elements.
Claim 2
Dependent Claim
232 words
In a method for adjusting the tap coefficient of an adaptive automatic equalizer having a plurality of tapped registers comprising the steps of: applying an input signal repetitively to a train of tapped delay elements; obtaining a sum of the weighted output of each tap output; obtaining an error output by taking the difference between the sum of the weighted output of each tap output and a reference signal; and obtaining a correlation value between said error output and each tap output of said delay elements; the improvement comprising: storing the tap weights of each of said tapped registers; obtaining the total sum of each tap weight of one of said tapped registers wherein the weight of a tap is said correlation value; repeating M times, where M is an integer, the obtaining the total sum of each tap weight in another of said tapped registers; adding said error output to said total sum; determining the value of a tap coefficient by the final total sum after M adjustments for the most rapid equalization; obtaining the optimum coefficient using said value of said top coefficient for the most rapid equalization of said tapped registers; and revising the weight of the taps of said delay elements by the optimum coefficient-weight-sum of the contents of said tapped register and said tapped delay elements, thereby adjusting the weight of each tap of said delay elements.
Claim 3
Dependent Claim
14 words
The invention as defined in claim 1, wherein said value of M is 1.
Claim 4
Dependent Claim
14 words
The invention as defined in claim 1, wherein said value of M is 2.
Claim 5
Dependent Claim
291 words
An adaptive automatic equalizer comprising: (a) an input terminal, for receiving an input signal, (b) a plurality of registers, (c) a plurality of convolution units for calculating the convolution between the input signal and the content of one of said registers, (d) a train of delay elements having a plurality of taps at each delay interval T, which is equal to the pulse interval of the input signal, (e) an α computer means for computing the value (α) of the tap adjustment coefficient from the output of the convolution units, (f) a plurality of multipliers for obtaining the product of the output of said delay elements and the output of said convolution units; (g) a plurality of integrators having the inputs thereof connected to the output of the multipliers, (h) changing means for changing the contents of each of said registers according to the output of said α computer means the outputs of said integrators and the precedent content of said registers, (i) a low speed clock pulse generator, the frequency of which is the same as the sampling frequency on a transmission line, for operating said registers, convolution units, a train of delay elements and said integrators, (j) a high speed clock pulse generator for operating said α computer means, said multipliers and changing means during a pair of low speed clock pulses in every MN low speed clock pulses, where M is an integer and N is a number of taps of said delay elements wherein said low speed clock pulse generator and said high speed clock pulse generator provide timing signals to said α computer means, and (k) an output terminal connected to the output of one of said convolution units for providing the output of said equalizer.
Claim 6
Dependent Claim
291 words
An adaptive automatic equalizer comprising: (a) an input terminal, for receiving an input signal, (b) a plurality of registers, (c) a plurality of convolution units for calculating the convolution between the input signal and the content of one of said registers, (d) a train of delay elements having a plurality of taps at each delay interval T, which is equal to the pulse interval of the input signal, (e) an α computer means for computing the value (α) of the tap adjustment coefficient from the output of the convolution units, (f) a plurality of multipliers for obtaining the product of the output of said delay elements and the output of said convolution units; (g) a plurality of integrators having the inputs thereof connected to the output of the multipliers, (h) changing means for changing the contents of each of said registers according to the output of said α computer means the outputs of said integrators and the precedent content of said registers, (i) a low speed clock pulse generator, the frequency of which is the same as the sampling frequency on a transmission line, for operating said registers, convolution units, a train of delay elements and said integrators, (j) a high speed clock pulse generator for operating said α computer means, said multipliers and changing means during a pair of low speed clock pulses in every MN low speed clock pulses, where M is an integer and N is a number of taps of said delay elements wherein said low speed clock pulse generator and said high speed clock pulse generator provide timing signals to said α computer means, and (k) an output terminal connected to the output of one of said convolution units for providing the output of said equalizer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-19 | 1982-09-18 | 1983-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-19 | 1986-09-18 | 1987-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-19 | 1990-09-18 | 1991-03-20 | $7700.00 | Window Closed / Lapsed |