US4064397A
Expired / Lapsed
US
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Automatic equalizer having a coefficient matrix circuit
Assignee: KDDI Corp
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Filing: 1976-06-24
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Granted: 1977-12-20
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Expires: 1996-06-24
Abstract
Abstract In an automatic equalizer for regenerating a received digital signal, comprising a delay element train with a plurality of taps, a coefficient matrix circuit and a group of variable coefficient units, the structure of said coefficient matrix circuit being considerably simplified by introducing a simple adder and/or subtractor at the input and/or the output of said coefficient matrix circuit.
Inventors
- 👤 Hiroshi Sakaki
- 👤 Sotokichi Shintani
- 👤 Hidemi Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:37
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03165; H04L2025/03433; H04L2025/03439; H04L2025/03445; H04L2025/03464
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
147 words
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of adders and subtractors, multipliers providing a product of each tap output of a group of variable coefficient and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps of said delay element train.
Claim 2
Dependent Claim
147 words
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of adders and subtractors, multipliers providing a product of each tap output of a group of variable coefficient and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps of said delay element train.
Claim 3
Dependent Claim
19 words
An automatic equalizer according to claim 1, wherein the number of taps of the delay element train is four.
Claim 4
Dependent Claim
33 words
An automatic equalizer according to claim 2, wherein the coefficient matrix is ##EQU14## where P ij (i=1,2, j=1,2,3,4) are scalar and can be arbitrarily chosen, and P s is 4 × 4 matrix.
Claim 5
Dependent Claim
198 words
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of multipliers and adders and subtractors, said multipliers providing a product of each tap output of said train and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit through a plurality of adders and subtractors, for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps situated symmetrically at said delay element train through said multipliers, a plurality of adders and subtractors provided at the output of said coefficient matrix circuit, said adders and subtractors comprising a transposed matrix of the matrix comprising the adders and subtractors at the input of said coefficient matrix circuit.
Claim 6
Dependent Claim
198 words
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of multipliers and adders and subtractors, said multipliers providing a product of each tap output of said train and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit through a plurality of adders and subtractors, for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps situated symmetrically at said delay element train through said multipliers, a plurality of adders and subtractors provided at the output of said coefficient matrix circuit, said adders and subtractors comprising a transposed matrix of the matrix comprising the adders and subtractors at the input of said coefficient matrix circuit.
Claim 7
Dependent Claim
19 words
An automatic equalizer according to claim 4, wherein the number of taps of the delay element train is four.
Claim 8
Dependent Claim
42 words
An automatic equalizer according to claim 5, wherein the coefficient matrix is ##EQU15## where ##EQU16## r' and s' being the transposed matrixes of r and s respectively, where P ij (i=1,2, j=1,2,3,4) are scalar, r and s are (2 = 2) matrixes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-19 | 1981-06-20 | 1981-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-19 | 1985-06-20 | 1985-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-19 | 1989-06-20 | 1989-12-20 | $7700.00 | Window Closed / Lapsed |