Multi-channel video switch using dual-gate MOS-FETS

Claim 1

A video signal switching circuit for alternately coupling first and second video signal paths to a third video signal path in response to a high-frequency, a switching signal means for generating a square-wave switching signal having a lower switching voltage level and a higher switching voltage level comprising: first and second dual-gate metal oxide semiconductor field effect transistors, each of said transistors having first and second gate terminals and having a source-drain path with a first and second terminal; said first terminals of source-drain paths of said first and second dual-gate transistors respectively coupled to said first and second video signal paths; said second terminals of said source-drain paths of said dual-gate transistors coupled to each other and to said third video path; said first gate terminal of said first dual-gate transistor coupled to said switching signal means; voltage potential means coupled to each of said second gates of said dual-gate transistors; a switching signal phase inversion means coupled to said switching signal means; and said first gate terminal of said second dual-gate transistor coupled to said switching signal phase inversion means wherein said switching signal phase inversion means comprises: a three terminal transistor with base terminal connected directly to said switching signal; an emitter resistor with a terminal connected to the emitter terminal of said three-terminal transistor and with another terminal connected to a zero voltage reference; a collector resistor of equal resistive value to said emitter resistor with a terminal connected to the collector terminal of said three-terminal transistor and with another terminal connected to a voltage potential equal to at least twice said higher voltage level; a zener diode having a breakdown voltage substantially equal to the value of said voltage potential less the sum of said lower switching voltage level and said higher switching voltage level with cathode terminal of said diode also connected to said collector terminal of said three-terminal transistor and with anode terminal of said diode connected to said first gate terminal of said second dual-gate transistor; and a zener-conduction resistor having one terminal also connected to said anode terminal of said diode and having another terminal connected to said zero voltage reference.