DTMF and rotary dial signal receiver

Claim 2

A dial signal receiver for receiving and decoding DTMF and rotary dial-type digit signals of the type produced by telephones and transmitted on telephone lines, said receiver comprising: a DTMF subsystem for: (i) receiving the high and low frequency components of a DTMF signal; (ii) determining if the frequency of each of said components is valid by performing independent short and long term frequency checks on each component; and, (iii) if both of said components are found to be valid, producing a DTMF digital code related to the nature of said DTMF signal; a rotary dial subsystem for: (i) receiving a signal denoting the presence and absence of telephone line loop current; (ii) determining if breaks in loop current, indicated by the absence of loop current, denote a valid rotary dial-type pulse train by measuring loop current intervals, and the restoration intervals between loop current break intervals; and, (iii) if a pulse train is found to be valid, producing a rotary dial digital code related to the number of pulses forming said pulse train; a main controller for receiving external control signals adapted to control the inhibiting of the operation of said DTMF subsystem and said rotary dial subsystem, said main controller connected to said DTMF subsystem and said rotary dial subsystem for inhibiting the operation of said DTMF subsystem and said rotary dial subsystem in accordance with said external control signals; and, an output register and decoder connected to said DTMF and said rotary dial subsystems for: (i) receiving said DTMF digital codes produced by said DTMF subsystem and said rotary dial digital codes produced by said rotary dial subsystem; and, (ii) producing an output digital code in accordance therewith.

Claim 3

A dial signal receiver as claimed in claim 1 wherein said output register and decoder is adapted to receive external format control signals, said external format control signals controlling the format of said output digital code.

Claim 4

A dial signal receiver as claimed in claim 2 wherein said high and low frequency short term frequency checks are continuously performed while said high and low frequency long term frequency checks are being performed.

Claim 5

A dial signal receiver as claimed in claim 3 wherein said DTMF subsystem is adapted to receive an early split control signal and, in accordance therewith, produce an early split output signal soon after a selected one of said high and low frequency components passes its first short term frequency check.

Claim 6

A dial signal receiver as claimed in claim 4 wherein said DTMF subsystem comprises: a high frequency channel circuit for performing said short and long term frequency checks on the high frequency component of said DTMF telephone signal; and, a low frequency channel circuit for performing said short and long term frequency checks on the low frequency component of said DTMF telephone signal.

Claim 7

A dial signal receive as claimed in claim 5 wherein said high and low frequency channel circuits are cross connected such that the failure of either of said short and long term frequency checks by either of said high and low frequency components causes both of said high and low frequency channel circuits to be reset.

Claim 8

A dial signal receiver as claimed in claim 6 wherein: said DTMF susbsystem includes a DTMF digit timing circuit, said DTMF digit timing circuit adapted to receive said external early split control signal and a condition signal denoting the line split status of a related telephone and, if said condition signal denotes that said line is not split, produce a simulate two-cycle signal, said simulate two-cycle signal being applied to said high and low frequency channel circuits; said high frequency channel circuit high frequency simulate means, responsive to said simulate two-cycle signal, for causing said high frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable high frequency signal were being received, during the period of time said simulate two-cycle is being generated, regardless of the exact nature of any received high frequency component; and, said low frequency channel circuit includes low frequency simulate means, responsive to said simulate two-cycle signal, for causing said low frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable low frequency signal were being received, during the period of time said simulate two-cycle signal is being generated, regardless of the exact nature of any received low frequency component.

Claim 9

A dial signal receiver as claimed in claim 7 wherein: (A) said high frequency channel circuit comprises: (1) a high frequency two-cycle circuit suitable for receiving said high frequency components and, in accordance therewith, produce a high frequency pulse chain having a frequency equal to one-half the frequency off said high frequency component; (2) a high frequency short term test circuit connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the intervals between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said high frequency component; (3) a high frequency long term counter connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train and produce a series of window control signals starting at predetermined intervals after the first pulse of a high frequency pulse train is received by said high frequency long term counter; and, (4) a high frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said high frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said high frequency pulse train, said window enabling signal applied to an enabling input of said gate, said gate also connected to said high frequency two-cycle circuit for receiving said high frequency pulse train, said gate passing a pulse of said high frequency pulse train if a pulse occurs during the period of time said gate in enabled by said window enabling signal, said pulse indicating that said high frequency component has passed both of said short and long term check; and, (B) said low frequency channel circuit comprises: (1) a low frequency two-cycle circuit suitable for receiving said low frequency components and, in accordance therewith, produce a low frequency pulse chain having a frequency equal to one-half the frequency of said low frequency component; (2) a low frequency short term test circuit connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the interval between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said low frequency component; (3) a low frequency long term counter to said low frequency two-cycle circuit so as to receive said low frequency pulse train and produce a series of low frequency window control signals starting at predetermined intervals after the first pulse of said low frequency pulse train is received by said low frequency long term counter; and, (4) a low frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said low frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said low frequency pulse train, said window enabling signal being applied to the enabling input of said gate, said gate also connected to said low frequency two-cycle circuit for receiving said low frequency pulse train, said gate passing a pulse of said low frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said low frequency component has passed both of said short and long term checks.

Claim 10

A dial signal receiver as claimed in claim 8 wherein: said high frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said high frequency long term test circuit; said low frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said low frequency long term test circuit; said DTMF digit timing circuit is connected to said high and low frequency long term test circuits so as to detect the setting of the latches of said high and low frequency long term test circuits, said DTMF digit timing circuit including means for producing a strobe signal when the latches of both of said high and low frequency long term test circuits are set; and, said output register and decoder is connected to said DTMF digit timing circuit so as to receive said strobe signal, said strobe signal causing said output register and decoder to read and decode said portions of said DTMF digital code produced by said high and low frequency short term test circuits.

Claim 11

A dial signal receiver as claimed in claim 9 wherein said DTMF digit timing circuit also includes means for producing a dual tone accept signal when said latches of said high and low frequency long term test circuits are both detected as set.

Claim 12

A dial signal receiver as claimed in claim 10 wherein said rotary dial subsystem comprises: a loop current timer connected to receive said signal denoting the presence or absence of telephone line loop current, said loop current timer producing a series of timing signals, and series of timing signals starting anew each time an absence of loop current is first detected and each time restoration of loop current is first detected; a rotary dial controller connected to receive the timing signals produced by said loop current timer and, based thereon, determine whether or not loop current break intervals and restoration intervals, denoted by the absence and presence of loop current, respectively, denote the receipt of a valid dial pulse train and, in accordance therewith, produce an output pulse for each valid rotary dial pulse contained in a rotary dial pulse train determined to be valid; and, a dial pulse counter connected to said rotary dial controller for counting the output pulses produced by said rotary dial controller, said dial pulse counter producing said rotary dial digital code applied to said output register and decoder.

Claim 13

A dial signal receiver as claimed in claim 11 wherein: said rotary dial controller also produces a signal denoting the receipt of valid rotary dial pulses upon the receipt and detection of valid rotary pulses; said DTMF digit timing circuit is connected to receive the signal produced by said rotary dial controller denoting the receipt of valid rotary dial pulses and, in accordance therewith, produce a strobe pulse identical to the strobe pulse produced when said latches of said high and low frequency long term counters are both detected as set; said main controller includes means for producing a data selection signal in accordance with whether or not said DTMF subsystem is receiving high and low frequency components of a DTMF signal or said rotary dial subsystem is receiving a signal denoting the presence and absence of telephone line loop current, said data selection signal being applied to said output register and decoder; said output register and decoder being conditioned by the data selection signal produced by said main controller so as to receive and store either said DTMF digital code or said rotary dial digital code depending upon the nature of said data selection signal; and, said strobe signal, produced by said DTMF digit timin circuit when said DTMF digit timing circuit receives a signal from said rotary dial controller denoting the receipt of a valid rotary dial pulse train or detects that the latches of said high and low frequency long term test circuits are both set, controlling the actual reading of a DTMF digital code or a rotay dial digital code by said output register and decoder.

Claim 14

A dial signal receiver as claimed in claim 1 wherein said high and low frequency short term frequency checks are continuously performed while said high and low frequency long term frequency checks are being performed.

Claim 15

A dial signal receiver as claimed in claim 13 wherein said DTMF subsystem is adapted to receive an early split control signal and, in accordance therewith, produce an early split output signal soon after a selected one of said high and low frequency components passes its first short term frequency check.

Claim 16

A dial signal receiver as claimed in claim 14 wherein said DTMF subsystem comprises: a high frequency channel circuit for performing said short and long term frequency checks on the high frequency component of said DTMF telephone signal; and, a low frequency channel circuit for performing said short and long term frequency checks on the low frequency component of said DTMF telephone signal.

Claim 17

A dial signal receiver as claimed in claim 15 wherein said high and low frequency channel circuits are cross connected such that the failure of either of said short and long term frequency checks by either of said high and low frequency components causes both of said high and low frequency channel circuits to be reset.

Claim 18

A dial signal receiver as claimed in claim 16 wherein: said DTMF subsystem includes a DTMF digit timing circuit, said DTMF digit timing circuit adapted to receive said external early split control signal and a condition signal denoting the line split status of a related telephone and, if said condition signal denotes that said line is not split, produce a simulate two-cycle signal, said simulate two-cycle signal being applied to said high and low frequency channel circuits; said high frequency channel circuit includes high fequency simulate means, responsive to said simulate two-cycle signal, for causing said high frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable high frequency signal were being received, during the period of time said simulate two-cycle is being generated, regardless of the exact nature of any received high frequency component; and, said low frequency channel circuit includes low frequency simulate means, resposive to said simulate two-cycle signal, for causing said low frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable low frequency signal were being received, during the period of time said simulate two-cycle signal is being generated, regardless of the exact nature of any received low frequency component.

Claim 19

A dial signal receiver as claimed in claim 17 wherein: (A) said high frequency channel circuit comprises: (1) a high frequency two-cycle circuit suitable for receiving said high frequency components and, in accordance therewith, produce a high frequency pulse chain having a frequency equal to one-half the frequency of said high frequency component; (2) a high frequency short term test circuit connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the intervals between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said high frequency component; (3) a high frequency long term counter connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train and produce a series of window control signals starting at predetermined intervals after the first pulse of a high frequency pulse train is received by said high frequency long term counter; and, (4) a high frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said high frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said high frequency pulse train, said window enabling signal applied to an enabling input of said gate, said gate also connected to said high frequency two-cycle circuit for receiving said high frequency pulse train, said gate passing a pulse of said high frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said high frequency component has passed both of said short and long term checks; and, (B) said low frequency channel circuit comprises: (1) a low frequency two-cycle circuit suitable for receiving said low frequency components and, in accordance therewith, produce a low frequency pulse chain having a frequency equal to one-half the frequency of said low frequency component; (2) a low frequency short term test circuit connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the interval between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said low frequency component; (3) a low frequency long term counter connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train and produce a series of low frequency window control signals starting at predetermined intervals after the first pulse of said low frequency pulse train is received by said low frequency long term counter; and, (4) a low frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said low frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said low frequency pulse train, said window enabling signal being applied to the enabling input of said gate, said gate also connected to said low frequency two-cycle circuit for receiving said low frequency pulse train, said gate passing a pulse of said low frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said low frequency component has passed both of said short and long term checks.

Claim 20

A dial signal receiver as claimed in claim 18 wherein: said high frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said high frequency long term test circuit; said low frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said low frequency long term test circuit; said DTMF digit timing circuit is connected to said high and low frequency long term test circuits so as to detect the setting of the latches of said high and low frequency long term test circuits, said DTMF digit timing circuit including means for producing a strobe signal when the latches of both of said high and low frequency long term test circuits are set; and, said output register and decoder is connected to said DTMF digit timing circuit so as to receive said strobe signal, said strobe signal causing said output register and decoder to read and decode said portions of said DTMF digital code produced by said high and low frequency short term test circuits.

Claim 21

A dial signal receiver as claimed in claim 19 wherein said DTMF digit timing circuit also includes means for producing a dual tone accept signal when said latches of said high and low frequency long term test circuits are both detected as set.

Claim 22

A dial signal receiver as claimed in claim 20 wherein said rotary dial subsystem comprises: a loop current timer connected to receive said signal denoting the presence or absence of telephone line loop current, said loop current timer producing a series of timing signals, said series of timing signals starting anew each time as absence of loop current is first detected and each time restoration of loop current is first detected; a rotary dial controller connected to receive the timing signals produced by said loop current timer and, based thereon, determine whether or not loop current break intervals and restoration intervals, denoted by the absence and presence of loop current, respectively, denote the receipt of a valid rotary dial pulse train and, in accordance therewith, produce an output pulse for each valid rotary dial pulse contained in a rotary dial pulse train determined to be valid; and, a dial pulse counter connected to said rotary dial controller for counting the output pulses produced by said rotary dial controller, said dial pulse counter producing said rotary dial digital code applied to said output register and decoder.

Claim 23

A dial signal receiver as claimed in claim 21 wherein: said rotary dial controller also produces a signal denoting the receipt of valid rotary dial pulses upon the receipt and detection of valid rotary dial pulses; said DTMF digit timing circuit is connected to receive the signal produced by said rotary dial controller denoting the receipt of valid rotary dial pulses and, in accordance therewith, produce a strobe pulse identical to the strobe pulse produced when said latches of said high and low frequency long term counters are both detected as set; said main controller includes means for producing a data selection signal in accordance with whether or not said DTMF subsystem is receiving high and low frequency components of a DTMF signal or said rotary dial subsystem is receiving a signal denoting the presence and absence of telephone line loop current, said data selection signal being applied to said output register and decoder; said output register and decoder being conditioned by the data selection signal produced by said main controller so as to receive and store either said DTMF digital code or said rotary dial digital code depending upon the nature of said data selection signal; and, said strobe signal, produced by said DTMF digit timing circuit when said DTMF digit timing circuit receives a signal from said rotary dial controller denoting the receipt of a valid rotary dial pulse train or detects that the latches of said high and low frequency long term test circuits are both set, controlling the actual reading of a DTMF digital code or a rotary dial digital code by said output register and decoder.

Claim 24

A dial signal receiver as claimed in claim 1 wherein said DTMF subsystem is adapted to receive an early split control signal and, in accordance therewith, produce an early split output signal soon after a selected one of said high and low frequency components passes its first short term frequency check.

Claim 25

A dial signal receiver as claimed in claim 23 wherein said DTMF subsystem comprises: a high frequency channel circuit for performing said short and long term frequency checks on the high frequency component of said DTMF telephone signal; and, a low frequency channel circuit for performing said short and long term frequency checks on the low frequency component of said DTMF telephone signal.

Claim 26

A dial signal receiver as claimed in claim 24 wherein said high and low frequency channel circuits are cross connected such that the failure of either of said short and long term frequency checks by either of said high and low frequency components causes both of said high and low frequency channel circuits to be reset.

Claim 27

A dial signal receiver as claimed in claim 25 wherein: said DTMF susbsystem includes, a DTMF digit timing circuit, said DTMF digit timing circuit adapted to receive said external early split control signal and a condition signal denoting the line split status of a related telephone and, if said condition signal denotes that said line is not split, produce a simulate two-cycle signal, said simulate two-cycle signal being applied to said high and low frequency channel circuits; said high frequency channel circuit includes high frequency simulate means, responsive to said simulate two-cycle signal, for causing said high frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable high frequency signal were being received, during the period of time said simulate two-cycle is being generated, regardless of the exact nature of any received high frequency component; and, said low frequency channel circuit includes low frequency simulate means, responsive to said simulate two-cycle signal, for causing said low frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable low frequency signal were being received, during the period of time said simulate two-cycle signal is being generated, regardless of the exact nature of any received low frequency component.

Claim 28

A dial signal receiver as claimed in claim 26 wherein: (A) said high frequency channel circuit comprises: (1) a high frequency two-cycle circuit suitable for receiving said high frequency components and, in accordance therewith, produce a high frequency pulse chain having a frequency equal to one-half the frequency of said high frequency component; (2) a high frequency short term test circuit connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the intervals between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said high frequency component; (3) a high frequency long term counter connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train and produce a series of window control signals starting at predetermined intervals after the first pulse of a high frequency pulse train is received by said high frequency long term counter; and, (4) a high frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said high frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said high frequency pulse train, said window enabling signal applied to an enabling input of said gate, said gate also connected to said high frequency two-cycle circuit for receiving said high frequency pulse train, said gate passing a pulse of said high frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said high frequency component has passed both of said short and long term checks; and, (B) said low frequency channel circuit comprises: (1) a low frequency two-cycle circuit suitable for receiving said low frequency components and, in accordance therewith, produce a low frequency pulse chain having a frequency equal to one-half the frequency of said low frequency component; (2) a low frequency short term test circuit connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the interval between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said low frequency component; (3) a low frequency long term counter connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train and produce a series of low frequency window control signals starting at predetermined intervals after the first pulse of said low frequency pulse train is received by said low frequency long term counter; and, (4) a low frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said low frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said low frequency pulse train, said window enabling signal being applied to the enabling input of said gate, said gate also connected to said low frequency two-cycle circuit for receiving said low frequency pulse train, said gate passing a pulse of said low frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said low frequency component has passed both of said short and long term checks.

Claim 29

A dial signal receiver as claimed in claim 27 wherein: said high frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said high frequency long term test circuit; said low frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said low frequency long term test circuit; said DTMF digit timing circuit is connected to said high and low frequency long term test circuits so as to detect the setting of the latches of said high and low frequency long term test circuits, said DTMF digit timing circuit including means for producing a strobe signal when the latches of both of said high and low frequency long term test circuits are set; and, said output register and decoder is connected to said DTMF digit timing circuit so as to receive said strobe signal, said strobe signal causing said output register and decoder to read and decode said portions of said DTMF digital code produced by said high and low frequency short term test circuits.

Claim 30

A dial signal receiver as claimed in claim 28 wherein said DTMF digit timing circuit also includes means for producing a dual tone accept signal when said latches of said high and low frequency long term circuits are both detected as set.

Claim 31

A dial signal receiver as claimed in claim 29 wherein said rotary dial subsystem comprises: a loop current timer connected to receive said signal denoting the presence or absence of telephone line loop current, said loop current timer producing a series of timing signals, said series of timing signals starting anew each time an absence of loop current is first detected and each time restoration of loop current is first detected; a rotary dial controller connected to receive the timing signals produced by said loop current timer and, based thereon, determine whether or not loop current break intervals and restoration intervals, denoted by the absence and presence of loop current, respectively, denote the receipt of a valid rotary dial pulse train and, in accordance therewith, produce an output pulse for each valid rotary dial pulse contained in a rotary dial pulse train determined to be valid; and, a dial pulse counter connected to said rotary dial controller for counting the output pulses produced by said rotary dial controller, said dial pulse counter producing said rotary dial digital code applied to said output register and decoder.

Claim 32

A dial signal receiver as claimed in claim 30 wherein: said rotary dial controller also produces a signal denoting the receipt of valid rotary dial pulses upon the receipt and detection of valid rotary dial pulses; said DTMF digit timing circuit is connected to receive the signal produced by said rotary dial controller denoting the receipt of valid rotary dial pulses and, in accordance therewith, produce a strobe pulse identical to the strobe pulse produced when said latches of said high and low frequency long term counters are both detected as set; said main controller includes means for producing a data selection signal in accordance with whether or not said DTMF subsystem is receiving high and low frequency components of a DTMF signal or said rotary dial subsystem is receiving a signal denoting the presence and absence of telephone line loop current, said signal data selection signal being applied to said output register and decoder; said output register and decoder being conditioned by the data selection signal produced by said main controller so as to receive and store either said DTMF digital code or said rotary dial digital code depending upon the nature of said data selection signal; and, said strobe signal, produced by said DTMF digit timing circuit when said DTMF digit timing circuit receives a signal from said rotary dial controller denoting the receipt of a valid rotary dial pulse train or detects that the latches of said high and low frequency long term test circuits are both set, controlling the actual reading of a DTMF digital code or a rotary dial digital code by said output register and decoder.

Claim 33

A dial signal receiver as claimed in claim 1 wherein said DTMF subsystem comprises: a high frequency channel circuit for performing said short and long term frequency checks on the high frequency component of said DTMF telephone signal; and, a low frequency channel circuit for performing said short and long term frequency checks on the low frequency component of said DTMF telephone signal.

Claim 34

A dial signal receiver as claimed in claim 32 wherein said high and low frequency channel circuits are cross connected such that the failure of either of said short and long term frequency checks by either of said high and low frequency components causes both of said high and low frequency channel circuits to be reset.

Claim 35

A dial signal receiver as claimed in claim 33 wherein: said DTMF susbsystem includes a DTMF digit timing circuit, said DTMF digit timing circuit adapted to receive said external early split control signal and a condition signal denoting the line split status of a related telephone and, if said condition signal denotes that said line is not split, produce a simulate two-cycle signal, said simulate two-cycle signal being applied to said high and low frequency channel circuits; said high frequency channel circuit includes high frequency simulate means, responsive to said simulate two-cycle signal, for causing said high frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable high frequency signal were being received, during the period of time said simulate two-cycle is being generated, regardless of the exact nature of any received high frequency component; and, said low frequency channel circuit includes low frequency simulate means, responsive to said simulate two-cycle signal, for causing said low frequency channel circuit to operate in substantially the same manner as it would normally operate if an acceptable low frequency signal were being received, during the period of time said simulate two-cycle signal is being generated, regardless of the exact nature of any received low frequency component.

Claim 36

A dial signal receiver as claimed in claim 34 wherein: (A) said high frequency channel circuit comprises: (1) a high frequency two-cycle circuit suitable for receiving said high frequency components and, in accordance therewith, produce a high frequency pulse chain having a frequency equal to one-half the frequency of said high frequency component; (2) a high frequency short term test circuit connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the intervals between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said high frequency component; (3) a high frequency long term counter connected to said high frequency two-cycle circuit so as to receive said high frequency pulse train and produce a series of window control signals starting at predetermined intervals after the first pulse of a high frequency pulse train is received by said high frequency long term counter; and, (4) a high frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said high frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said high frequency pulse train, said window enabling signal applied to an enabling input of said gate, said gate also connected to said high frequency two-cycle circuit for receiving said high frequency pulse train, said gate passing a pulse of said high frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said high frequency component has passed both of said short and long term checks; and, (B) said low frequency channel circuit comprises: (1) a low frequency two-cycle circuit suitable for receiving said low frequency components and, in accordance therewith, produce a low frequency pulse chain having a frequency equal to one-half the frequency of said low frequency component; (2) a low frequency short term test circuit connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of said DTMF digital code as long as the interval between said adjacent pulses remains the same, said portion of said DTMF digital code being related to the frequency of said low frequency component; (3) a low frequency long term counter connected to said low frequency two-cycle circuit so as to receive said low frequency pulse train and produce a series of low frequency window control signals starting at predetermined intervals after the first pulse of said low frequency pulse train is received by said low frequency long term counter; and, (4) a low frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said low frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said low frequency pulse train, said window enabling signal being applied to the enabling input of said gate, said gate also connected to said low frequency two-cycle circuit for receiving said low frequency pulse train, said gate passing a pulse of said low frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said low frequency component has passed both of said short and long term checks.

Claim 37

A dial signal receiver as claimed in claim 35 wherein: said high frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said high frequency long term test circuit; said low frequency long term test circuit includes a latch that is set when said pulse is passed by the gate of said low frequency long term test circuit; said DTMF digit timing circuit is connected to said high and low frequency long term test circuits so as to detect the setting of the latches of said high and low frequency long term test circuits, said DTMF digit timing circuit including means for producing a strobe signal when the latches of both of said high and low frequency long term test circuits are set; and, said output register and decoder is connected to said DTMF digit timing circuit so as to receive said strobe signal, said strobe signal causing said output register and decoder to read and decode said portions of said DTMF digital code produced by said high and low frequency short term test circuits.

Claim 38

A dial signal receiver as claimed in claim 36 wherein said DTMF digit timing circuit also includes means for producing a dual tone accept signal when said latches of said high and low frequency long term test circuits are both detected as set.

Claim 39

A dial signal receiver as claimed in claim 37 wherein said rotary dial subsystem comprises: a loop current timer connected to receive said signal denoting the presence or absence of telephone line loop current, said loop current timer producing a series of timing signals, said series of timing signals starting anew each time an absence of loop current is first detected and each time restoration of loop current is first detected; a rotary dial controller connected to receive the timing signals produced by said loop current timer and, based thereon, determine whether or not loop current break intervals and restoration intervals, denoted by the absence and presence of loop current, respectively, denote the receipt of a valid rotary dial pulse train and, in accordance therewith, produce an output pulse for each valid rotary dial pulse contained in a rotary dial pulse train determined to be valid; and, a dial pulse counter connected to said rotary dial controller for counting the output pulses produced by said rotary dial controller, said dial pulse counter producing said rotary dial digital code applied to said output register and decoder.

Claim 40

A dial signal receiver as claimed in claim 38 wherein: said rotary dial controller also produces a signal denoting the receipt of valid rotary dial pulses upon the receipt and detection of valid rotary dial pulses; said DTMF digit timing circuit is connected to receive the signal produced by said rotary dial controller denoting the receipt of valid rotary dial pulses and, in accordance therewith, produce a strobe pulse identical to the strobe pulse produced when said latches of said high and low frequency long term counters are both detected as set; said main controller includes means for producing a data selection signal in accordance with whether or not said DTMF subsystem is receiving high and low frequency components of a DTMF signal or said rotary dial subsystem is receiving a signal denoting the presence and absence of telephone line loop current, said signal data selection signal being applied to said output register and decoder; said output register and decoder being conditioned by the data selection signal produced by said main controller so as to receive and store either said DTMF digital code or said rotary dial digital code depending upon the nature of said data selection signal; and, said strobe signal, produced by said DTMF digit timing circuit when said DTMF digit timing circuit receives a signal from said rotary dial controller denoting the receipt of a valid rotary dial pulse train or detects that the latches of said high and low frequency long term test circuits are both set, controlling the actual reading of a DTMF digital code or a rotary dial digital code by said output register and decoder.

Claim 41

A dial signal receiver as claimed in claim 1 wherein said rotary dial subsystem comprises: a loop current timer connected to receive said signal denoting the presence or absence of telephone line loop current, said loop current timer producing a series of timing signals, said series of timing signals starting anew each time an absence of loop current is first detected and each time restoration of loop current is first detected; a rotary dial controller connected to receive the timing signals produced by said loop current timer and, based thereon, determine whether or not loop current break intervals and restoration intervals, denoted by the absence and presence of loop current, respectively, denote the receipt of a valid rotary dial pulse train and, in accordance therewith, produce an output pulse for each valid rotary dial pulse contained in a rotary dial pulse train determined to be valid; and, a dial pulse counter connected to said rotary dial controller for counting the output pulses produced by said rotary dial controller, said dial pulse counter producing said rotary dial digital code applied to said output register and decoder.

Claim 42

A dial signal receiver as claimed in claim 40 wherein: said rotary dial controller also produces a signal denoting the receipt of valid rotary dial pulses upon the receipt and detection of valid rotary dial pulses; said DTMF subsystem includes a DTMF digit timing circuit connected to receive the signal produced by said rotary dial controller denoting the receipt of valid rotary dial pulses and, in accordance therewith, produce a strobe pulse; and, said output register and decoder is connected to said DTMF digit timing circuit so as to receive said strobe signal, said strobe signal enabling said output register and decoder to read and decode said rotary dial digital code produced by said dial pulse counter.

Claim 43

A dial signal receiver as claimed in claim 41 wherein said output register and decoder is adapted to receive external format control signals, said external format control signals controlling the format of said output digital code.

Claim 44

A dial signal receiver as claimed in claim 40 wherein said output register and decoder is adapted to receive external format control signals, said external format control signals controlling the format of said output digital code.

Claim 45

A dial signal receiver for receiving and detecting multiple frequency signals including at least two discrete components, said dial signal receiver comprising: a first frequency channel circuit for performing independent short and long term frequency checks on a first frequency component of said multiple frequency signal; and, a second frequency channel circuit for performing independent short and long term frequency checks on a second frequency component of said multiple frequency signal, said first and second channel circuits being cross connected such that the failure of either of said short and long term frequency checks by either of said first and second frequency components causes both of said first and second frequency channel circuits to be reset, said first and second frequency channel circuits producing an output signal denoting the receipt of a valid multiple frequency signal only if said first and second frequency components of said multiple frequency signal pass both of said short and long term frequency checks.

Claim 46

A dial signal receiver for receiving and detecting multiple frequency signals including at least two discrete components, said dial signal receiver comprising: a first frequency channel circuit for performing independent short and long term frequency checks on a first frequency component of said multiple frequency signal; and, a second frequency channel circuit for performing independent short and long term frequency checks on a second frequency component of said multiple frequency signal, said first and second channel circuits being cross connected such that the failure of either of said short and long term frequency checks by either of said first and second frequency components causes both of said first and second frequency channel circuits to be reset, said first and second frequency channel circuits producing an output signal denoting the receipt of a valid multiple frequency signal only if said first and second frequency components of said multiple frequency signal pass both of said short and long term frequency checks.

Claim 47

A dial signal receiver as claimed in claim 44 wherein: (A) said first frequency channel circuit comprises: (1) a first frequency pulse circuit suitable for receiving said first frequency components and, in accordance therewith, produce a first frequency pulse chain having a frequency related to the frequency of said first frequency component; (2) a first frequency short term test circuit connected to said first frequency pulse circuit so as to receive said first frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of a frequency digital code as long as the intervals between said adjacent pulses remains the same, said portion of said frequency digital code being related to the frequency of said first frequency component; (3) a first frequency long term counter connected to said first frequency pulse circuit so as to receive said first frequency pulse train and produce a series of window control signals starting at predetermined intervals after the first pulse of a first frequency pulse train is received by said first frequency long term counter; and, (4) a first frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said first frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said first frequency pulse train, said window enabling signal applied to an enabling input of said gate, said gate also connected to said first frequency pulse circuit for receiving said first frequency pulse train, said gate passing a pulse of said first frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said first frequency component has passed both of said short and long term checks; and, (B) said second frequency channel circuit comprises: (1) a second frequency pulse circuit suitable for receiving said second frequency components and, in accordance therewith, produce a second frequency pulse chain having a frequency related to the frequency of said second frequency component; (2) a second frequency short term test circuit connected to said second frequency pulse circuit so as to receive said second frequency pulse train, continuously compare the intervals between adjacent pulses of said pulse train and produce a portion of a frequency digital code as long as the interval between said adjacent pulses remains the same, said portion of said frequency digital code being related to the frequency of said second frequency component; (3) a second frequency long term counter connected to said second frequency pulse circuit so as to receive said second frequency pulse train and produce a series of second frequency window control signals starting at predetermined intervals after the first pulse of said second frequency pulse train is received by said second frequency long term counter; and, (4) a second frequency long term test circuit including a gate and a gate enabling subsystem, said gate enabling subsystem connected to said second frequency long term counter for receiving said window control signals and creating, in accordance therewith, a window enabling signal, said window enabling signal being related to the frequency of said second frequency pulse train, said window enabling signal being applied to the enabling input of said gate, said gate also connected to said second frequency pulse circuit for receiving said second frequency pulse train, said gate passing a pulse of said second frequency pulse train if a pulse occurs during the period of time said gate is enabled by said window enabling signal, said pulse indicating that said second frequency component has passed both of said short and long term checks.