Multifrequency-to-digital converter

Claim 2

A multifrequency-to-digital converter comprising: 1. receiving means for receiving a multifrequency signal including at least two components having different frequencies; 2. separating means connected to said receiving means for separating said received multifrequency signal into said at least two components having different frequencies; and 3. conversion means connected to said separating means for converting said at least two components into a digital signal representing said at least two components, said conversion means comprising: a. bandpass means connected to said separating means for determining whether said at least two components are within predetermined frequency ranges; b. detecting means connected to said bandpass means for detecting when said bandpass means has determined that said two components are within said predetermined frequency ranges; c. counting means adapted to receive pulses and connected to said detecting means for counting pulses over a predetermined number of cycles of said at least two components, said counting starting when said bandpass means determins that said components are within said predetermined frequency ranges; and, d. decoding means connected to said counting means for decoding the number of pulses counted by said counting means over said predetermined number of cycles and, in accordance therewith, generating a digital signal related to said received multifrequency signal, said decoding means including memory means for storing a plurality of different pulse counts; and, comparing means for sequentially comparing the pulse counts stored by said memory means with the pulse counts counted by said counting means and for generating an output signal when a comparison, within a predetermined range is found.

Claim 3

A multifrequency-to-digital converter as claimed in claim 1 wherein one of said at least two components is a high frequency component and wherein the other of said two components is a low frequency component.

Claim 4

separating means connected to said receiving means for separating said received multifrequency signal into said at least two components having different frequencies; and

Claim 5

separating means connected to said receiving means for separating said received multifrequency signal into said at least two components having different frequencies; and

Claim 6

detecting means connected to said bandpass means for detecting when said bandpass means has determined that said two components are within said predetermined frequency ranges;

Claim 7

detecting means connected to said bandpass means for detecting when said bandpass means has determined that said two components are within said predetermined frequency ranges;

Claim 8

counting means adapted to receive pulses and connected to said detecting means for counting pulses over a predetermined number of cycles of said two components, said counting starting when said bandpass means determines that said components are within said predetermined frequency ranges; and,

Claim 9

counting means adapted to receive pulses and connected to said detecting means for counting pulses over a predetermined number of cycles of said two components, said counting starting when said bandpass means determines that said components are within said predetermined frequency ranges; and,

Claim 10

conversion means connected to said separating means for converting said at least two components into a digital signal representing said at least two components, said conversion means comprising: a. bandpass means connected to said separating means for determining whether said at least two components are within predetermined frequency ranges; b. detecting means connected to said bandpass means for detecting when said bandpass means has determined that said two components are within said predetermined frequency ranges; c. counting means adapted to receive pulses and connected to said detecting means for counting pulses over a predetermined number of cycles of said at least two components, said counting starting when said bandpass means determins that said components are within said predetermined frequency ranges; and, d. decoding means connected to said counting means for decoding the number of pulses counted by said counting means over said predetermined number of cycles and, in accordance therewith, generating a digital signal related to said received multifrequency signal, said decoding means including memory means for storing a plurality of different pulse counts; and, comparing means for sequentially comparing the pulse counts stored by said memory means with the pulse counts counted by said counting means and for generating an output signal when a comparison, within a predetermined range is found.

Claim 11

conversion means connected to said separating means for converting said at least two components into a digital signal representing said at least two components, said conversion means comprising: a. bandpass means connected to said separating means for determining whether said at least two components are within predetermined frequency ranges; b. detecting means connected to said bandpass means for detecting when said bandpass means has determined that said two components are within said predetermined frequency ranges; c. counting means adapted to receive pulses and connected to said detecting means for counting pulses over a predetermined number of cycles of said at least two components, said counting starting when said bandpass means determins that said components are within said predetermined frequency ranges; and, d. decoding means connected to said counting means for decoding the number of pulses counted by said counting means over said predetermined number of cycles and, in accordance therewith, generating a digital signal related to said received multifrequency signal, said decoding means including memory means for storing a plurality of different pulse counts; and, comparing means for sequentially comparing the pulse counts stored by said memory means with the pulse counts counted by said counting means and for generating an output signal when a comparison, within a predetermined range is found.

Claim 12

A multifrequency-to-digital converter as claimed in claim 2 wherein said bandpass means comprises: a low frequency bandpass counter connected to receive said low frequency component and generate a digital output related to the frequency of said low frequency components; a low frequency decoder connected to said low frequency bandpass counter for decoding the digital output of said low frequency bandpass counter and generating a signal related to whether or not said low frequency component is within a predetermined low frequency range; a high frequency bandpass counter connected to receive said high frequency component and generate a digital output related to the frequency of said high frequency component; and, a high frequency decoder connected to said high frequency bandpass counter for decoding the digital output of said high frequency bandpass counter and generating a signal related to whether or not said high frequency component is within a predetermined high frequency range.

Claim 13

A multifrequency-to-digital converter as claimed in claim 3 including a symmetry counter and decoder connected to receive one of said high and low frequency components and determine whether or not said one of said high and low frequency components is symmetrical and generate a signal related to whether or not said one of said high and low frequency components is symmetrical.

Claim 14

decoding means connected to said counting means for decoding the number of pulses counted by said counting means over said predetermined number of cycles and, in accordance therewith, generating a digital signal, said decoding means including memory means for storing a plurality of different pulse counts; and, comparing means for sequentially comparing the pulse counts stored by said memory means with the pulse counts counted by said counting means and for generating an output signal when a comparison, within a predetermined range, is found.

Claim 15

decoding means connected to said counting means for decoding the number of pulses counted by said counting means over said predetermined number of cycles and, in accordance therewith, generating a digital signal, said decoding means including memory means for storing a plurality of different pulse counts; and, comparing means for sequentially comparing the pulse counts stored by said memory means with the pulse counts counted by said counting means and for generating an output signal when a comparison, within a predetermined range, is found.

Claim 16

A multifrequency-to-digital converter as claimed in claim 4 wherein said counting means comprises: low frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said low frequency components; a low frequency cycle counter connected to said low frequency decoder for counting the number of cycles determined by said low frequency decoder to be within said predetermined low frequency range; a low frequency detect latch and control connected to said low frequency cycle counter and to said low frequency counting means for sensing when said low frequency cycle counter receives a signal from the low frequency decoder indicating that at least one cycle of the low frequency component has fallen within said predetermined low frequency range and causing said low frequency counting means to start counting pulses, and for determining when said low frequency cycle counter Determines that a predetermined number of cycles have fallen within said predetermined low frequency range and stopping said low frequency counter means from counting pulses; high frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said high frequency component; a high frequency cycle counter connected to said high frequency decoder for counting the number of cycles determined by said high frequency decoder to be within said predetermined high frequency range; and, a high frequency detect latch and control connected to said high frequency cycle counter and to said high frequency counting means for sensing when said high frequency cycle counter receives a signal from said high frequency decoder indicating that at least one cycle of said high frequency component has fallen within said predetermined high frequency range and causing said high frequency counting means to start counting pulses, and for determining when said high frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined high frequency range and stopping said high frequency counting means from counting pulses.

Claim 17

A multifrequency-to-digital converter as claimed in claim 5 wherein said symmetry counter and decoder determines whether cycles of said high frequency component are symmetrical and wherein said high frequency cycle counter is connected to said symmetry counter and decoder to receive the signal generated by said symmetry counter and decoder related to the number of high frequency cycles and count the number of high frequency cycles that are symmetrical.

Claim 18

A multifrequency-to-digital converter as claimed in claim 6 wherein said memory means comprises: a read-only memory for storing a plurality of binary words and for generating a parallel digital output related to each of said stored binary words in accordance with a control signal input; a read-only memory parallel to serial register connected to the parallel digital output of said read-only memory to receive and convert the parallel digital output of said read-only memory into a serial digital signal; and, read-only memory counting means suitable for counting clock pulses and for generating control signals suitable for controlling which of the binary words stored in said read-only memory is received by said read-only memory parallel-to-serial register.

Claim 19

A multifrequency-to-digital converter as claimed in claim 7 wherein said comparing means comprises: a decision logic circuit connected to said low and high frequency counting means and to said read-only memory parallel-to-serial register for comparing the counts in said high and low frequency counting means with the serial output of said ready-only parallel to serial register in a sequential manner so as to determine when a comparison exists; and, decoding apparatus connected to said read-only memory counting means and to said decision logic for decoding the control signal output of said read-only memory counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of one of said low frequency counting means and said high frequency counting means.

Claim 20

A multifrequency-to-digital converter as claimed in claim 8 wherein said decoding apparatus comprises: master latches connected to said read-only memory counting means for storing a predetermined portion of the control signal output generated by said read-only memory counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of one of said low frequency counting means and said high frequency counting means; a word file connected to said master latches for generating a work file signal in accordance with the portion of saiD control signal output stored by said master latches; and, an output decoder connected to said word file for generating a digital output on a plurality of lines in accordance with the work file signal generated by said word file.

Claim 21

A multifrequency-to-digital converter as claimed in claim 9 including a double detector and a power detector connected to said high and low frequency detect latches and controls for causing said high and low frequency detect latches and controls to recycle once the high and low frequency components have been found to be within said predetermined high and low frequency ranges for a predetermined number of cycles to determine for a second time whether or not the high and low frequency components fall within said predetermined high and low frequency ranges for a predetermined number of cycles.

Claim 22

A multifrequency-to-digital converter as claimed in claim 10 including: a low frequency edge detector connected so as to receive said low frequency components and detect the beginning thereof and apply a signal to said low frequency bandpass counter in accordance therewith; and a high frequency edge detector and synchronizing circuit connected so as to receive said high frequency component and to apply a signal to said high frequency bandpass counter in accordance therewith.

Claim 23

A multifrequency-to-digital converter as claimed in claim 11 wherein said read-only memory counting means comprises: a bit counter adapted to count clock pulses and generate pulse signals in accordance therewith; and, a read-only memory word counter adapted to count the pulse signals generated by said bit counter and, in accordance therewith, generate said control signal output, said bit counter and said read-only memory word counter being activated by an output from said double detector and power detector which occurs when said double detector and power detector determines that said high and low frequency components have proven to be within their respective predetermined ranges for two cycles of operation related to determining whether said high and low frequency components are within their respective predetermined ranges.

Claim 24

A multifrequency-to-digital converter as claimed in claim 3 wherein said counting means comprises: low frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said low frequency component; a low frequency cycle counter connected to said low frequency decoder for counting the number of cycles determined by said low frequency decoder to be within said predetermined low frequency range; a low frequency detect latch and control connected to said low frequency cycle counter and to said low frequency counting means for sensing when said low frequency cycle counter receives a signal from the low frequency decoder indicating that at least one cycle of the low frequency component has fallen within said predetermined low frequency range and causing said low frequency counting means to start counting pulses, and for determining when said low frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined low frequency range and stopping said low frequency counter means from counting pulses; high frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said high frequency component; a high frequency cycle counter connected to said high frequency decoder for counting the number of cycles determined by said high frequency decoder to be within said predetermined high frequency range; and, a high frequency detect latch and control connected to said high frequency cycle counter and to said high frequency counting means for sensing when said high frequency cycle counter receives a signal from said high frequency decoder indIcating that at least one cycle of said high frequency component has fallen within said predetermined high frequency range and causing said high frequency counting means to start counting pulses, and for determining when said high frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined high frequency and stopping said high frequency counting means from counting pulses.

Claim 25

A multifrequency-to-digital converter as claimed in claim 2 wherein said memory means comprises: a read-only memory for storing a plurality of binary words and for generating a parallel digital output related to each of said stored binary words in accordance with a control signal output; a read-only memory parallel-to-serial register connected to the parallel digital output of said read-only memory to receive and convert the parallel digital output of said read-only memory into a serial digital signal; and, read-only memory counting means suitable for counting clock pulses and for generating control signals suitable for controlling which of the binary words stored in said read-only memory is received by said read-only memory parallel-to-serial register.

Claim 26

A multifrequency-to-digital converter as claimed in claim 14 wherein said counting means comprises: low frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said low frequency component; a low frequency cycle counter connected to said low frequency decoder for counting the number of cycles determined by said bandpass means to be within said predetermined low frequency range; a low frequency detect latch and control connected to said low frequency cycle counter and to said low frequency counting means for sensing when said low frequency cycle counter receives a signal from said bandpass means indicating that at least one cycle of the low frequency component has fallen within said predetermined low frequency range and causing said low frequency counting means to start counting pulses, and for determining when said low frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined low frequency range and stopping said low frequency counter means from counting pulses; high frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said high frequency component; a high frequency cycle counter connected to said high frequency decoder for counting the number of cycles determined by said bandpass means to be within said predetermined high frequency range; and, a high frequency detect latch and control connected to said high frequency cycle counter and to said high frequency counting means for sensing when said high frequency cycle counter receives a signal from said bandpass means indicating that at least one cycle of said high frequency component has fallen within said predetermined high frequency range and causing said high frequency counting means to start counting pulses, and for determining when said high frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined high frequency range and stopping said high frequency counting means from counting pulses.

Claim 27

A multifrequency-to-digital conversion means as claimed in claim 15 wherein said comparing means comprises: a decision logic circuit connected to said low and high frequency counting means and to said read-only memory parallel-to-serial register for comparing the counts in said high and low frequency counting means with the serial output of said read-only parallel-to-serial register in a sequential manner so as to determine when a comparison exists; and, decoding apparatus connected to said counting means and to said decision logic for decodinG the control signal output of said counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of one of said low frequency counting means and said high frequency counting means.

Claim 28

A multifrequency-to-digital converter as claimed in claim 16 wherein said decoding apparatus comprises: master latches connected to said read-only memory counting means for storing a predetermined portion of the control signal output generated by said read-only memory counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of one of said low frequency counting means and said high frequency counting means; a word file connected to said master latches for generating a work file signal in accordance with the portion of said control signal output stored by said master latches; and, an output decoder connected to said word file for generating a digital output on a plurality of lines in accordance with the word file signal generated by said word file.

Claim 29

A multifrequency-to-digital converter for converting a two component multifrequency signal into a digital signal representing said two components, said multifrequency-to-digital converter comprising:

Claim 30

A multifrequency-to-digital converter for converting a two component multifrequency signal into a digital signal representing said two components, said multifrequency-to-digital converter comprising:

Claim 31

A multifrequency-to-digital converter is claimed in claim 18 wherein said bandpass means comprises: a first frequency bandpass counter connected to receive one of said components and generate a digital output related to the frequency of said component; a first frequency decoder connected to said first frequency bandpass counter for decoding the digital output of said first frequency bandpass counter and generating a signal related to whether or not said one of said frequency components is within a predetermined first frequency range; a second frequency bandpass counter connected to receive the other of said frequency components and generate a digital output related to the frequency of said component; and, a second frequency decoder connected to said second frequency bandpass counter for decoding the digital output of said second frequency bandpass counter and generating a signal related to whether or not said other of said frequency components is within a predetermined second frequency range.

Claim 32

A multifrequency-to-digital converter as claimed in claim 19 including a symmetry counter and decoder connected to receive one of said frequency components and determine whether or not said one of said frequency components is symmetrical and generate a signal related to whether or not said one of said frequency components is symmetrical.

Claim 33

A multifrequency-to-digital converter as claimed in claim 19 wherein said counting means comprises: firsT frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said one of said frequency components; a first frequency cycle counter connected to said first frequency decoder for counting the number of cycles determined by said first frequency decoder to be within said predetermined first frequency range; a first frequency detect latch and control connected to said first frequency cycle counter and to said first frequency counting means for sensing when said first frequency cycle counter receives a signal from the first frequency decoder indicating that at least one cycle of said one of said frequency components has fallen within said predetermined first frequency range and causing said first frequency counting means to start counting pulses, and for determining when said first frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined first frequency range and stopping said first frequency counting means from counting pulses; second frequency counting means adapted to count clock pulses and generate a serial output signal related to the number of clock pulses counted over a predetermined number of cycles of said other of said frequency components; a second frequency cycle counter connected to said second frequency decoder for counting the number of cycles determined by said second frequency decoder to be within said predetermined second frequency range; and, a second frequency detect latch and control connected to said second frequency cycle counter and to said second frequency counting means for sensing when said second frequency cycle counter receives a signal from said second frequency decoder indicating that at least one cycle of said other of said frequency components has fallen within said predetermined second frequency range and causing said frequency counting means to start counting pulses, and for determining when said second frequency cycle counter determines that a predetermined number of cycles have fallen within said predetermined second frequency range and stopping said second frequency counting means from counting pulses.

Claim 34

A multifrequency-to-digital converter as claimed in claim 21 wherein said memory means comprises: a read-only memory for storing a plurality of binary words and for generating a parallel digital output related to each of said stored binary words in accordance with a control signal input; a read-only memory parallel-to-serial register connected to the parallel digital output of said read-only memory to receive and convert the parallel digital output of said read-only memory into a serial digital signal; and, read-only memory counting means suitable for counting clock pulses and for generating control signals suitable for controlling which of the binary words stored in said read-only memory is received by said read-only memory parallel-to-serial register.

Claim 35

A multifrequency-to-digital conversion means as claimed in claim 22 wherein said comparing means comprises: a decision logic circuit connected to said first and second frequency counters and to said read-only memory parallel-to-serial register for comparing the counts in said first and second frequency counters with the serial output of said read-only parallel-to-serial register in a sequential manner so as to determine when a comparison exists; and, decoding apparatus connected to said read-only memory counting means and to said decision logic for decoding the control signal output of said read-only memory counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of one of said first frequency counting means and said second frequency counting means.

Claim 36

A multifrequency-to-digital converter as claimed in claim 23, wherein said decoding apparatus comprises: master latches connected to said read-only memory counting means for storing predetermined portions of the control signal output generated by said read-only memory counting means when said decision logic determines that a comparison exists between the output of said read-only memory parallel-to-serial register and the output of said first frequency counting means and said second frequency counting means; a word file connected to said master latches for generating a word file signal in accordance with the portion of said control signal output stored by said master latches; and, an output decoder connected to said word file for generating a digital output on a plurality of lines in accordance with the word file signal generated by said word file.

Claim 37

A multifrequency-to-digital converter as claimed in claim 24, including a double detector and a power detector connected to said first and second frequency detect latches and controls for causing said first and second frequency detect latches and controls to recycle once the first and second frequency components have been found to be within their respective predetermined frequency ranges for a predetermined number of cycles to determine for a second time whether or not the first and second frequency components fall with their respective predetermined frequency ranges for a predetermined number of cycles.