Patent US4144522A successfully refreshed from Google Patents.
US4144522A
Expired / Lapsed
US
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Electro-control system for data transmission
Assignee: Toshiba Corp
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Filing: 1977-02-24
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Granted: 1979-03-13
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Expires: 1997-02-24
Abstract
Abstract An error-control system for a continuous ARQ system, wherein, when a transmitter detects a dummy signal different from a negative acknowledgment signal caused by a channel noise appearing on a transmission channel, the transmitter supplies a receiver with a block signal comprising a designating number of a given block, a block data thereof and a check code formed by reversing a prescribed error detection code, thereby controlling the occurrence of an error in data transmission between the transmitting and receiving sides.
Inventors
- 👤 Satoshi Kageyama
- 👤 Kunihiko Sekiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:31
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/12; H04L1/16; H04L1/18; H04L1/1809; H04L1/1867; H04L2001/125
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
An error control system for transmission of data between a transmitter and a receiver, the transmitter comprising: means for transmitting successively a series of block signals each formed of data, a block number code and an error-detecting code to the receiver through a forward channel; means for detecting a negative acknowledgement including a block number designation designating a block signal in which an error is detected at the receiver means for detecting a false negative acknowledgement sent forth from the receiver; means for inverting all bits of a data signal or an error detecting code being transmitted upon detection of the negative acknowledgement; means for transmitting the inverted data signal or the error detecting code to the receiver; the receiver comprising: means for detecting an error from at least the data signal included in the block signals received and means for sending forth through a backward channel the negative acknowledgement upon detection of an error to cause the transmitter to again deliver block signals, the first one of which is a block signal corresponding to the block signal found erroneous.
Claim 2
Dependent Claim
180 words
An error control system for transmission of data between a transmitter and a receiver, the transmitter comprising: means for transmitting successively a series of block signals each formed of data, a block number code and an error-detecting code to the receiver through a forward channel; means for detecting a negative acknowledgement including a block number designation designating a block signal in which an error is detected at the receiver means for detecting a false negative acknowledgement sent forth from the receiver; means for inverting all bits of a data signal or an error detecting code being transmitted upon detection of the negative acknowledgement; means for transmitting the inverted data signal or the error detecting code to the receiver; the receiver comprising: means for detecting an error from at least the data signal included in the block signals received and means for sending forth through a backward channel the negative acknowledgement upon detection of an error to cause the transmitter to again deliver block signals, the first one of which is a block signal corresponding to the block signal found erroneous.
Claim 3
Dependent Claim
24 words
The error control system according to claim 1 wherein the inverting means includes means for inverting a predetermined number of bits of the data.
Claim 4
Dependent Claim
25 words
The error control system according to claim 1 wherein the inverting means includes means for inverting a predetermined number of bits of the error-detecting code.
Claim 5
Dependent Claim
19 words
The error control system according to claim 3 further comprising a continuous automatic repeat request system in combination therewith.
Claim 6
Dependent Claim
26 words
The error control system according to claim 1 wherein the inverting means includes means for inverting a predetermined number of bits of the block number code.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |