Patent AT100642B successfully refreshed from Google Patents.
US4144484A
Expired / Lapsed
US
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DC Voltage control device
Assignee: Panasonic Holdings Corp
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Filing: 1977-12-27
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Granted: 1979-03-13
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Expires: 1997-12-27
Abstract
Abstract A DC voltage control device comprising first and second R-S flip-flops, two diodes and an analog memory comprising a MOS field-effect transistor, a nonpolarized capacitor and an analog switch. The DC voltage may be increased, decreased and maintained at a desired level. Because of the analog memory, the signal level is stored or maintained even in case of power failure. The DC voltage control device may be used as a brightness control of an incandescent lamp, VCF (voltage controlled frequency) of a sweep generator and so on.
Inventors
- 👤 Shunji Minami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:33
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G05; G05F; G05F1/00; G05F1/10; G05F1/46
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
172 words
A DC voltage control device comprising (a) an analog memory comprising a MOS field-effect transistor, and a nonpolarized capacitor (b) a first R-S flip-flop connected to a first input terminal of said analog memory, (c) a second R-S flip-flop connected to a second input terminal of said analog memory, (d) a first diode connected between a second set input terminal of said second R-S flip-flop and a first set input terminal of said first R-S flip-flop, (e) a second diode connected between a second rest input terminal of said second R-S flip-flop and a first set input terminal of said first R-S flip-flop, (f) a down switch connected to said second set input terminal of said second R-S flip-flop, (g) an up switch connected to said second reset input terminal of said second R-S flip-flop, and (h) a stop switch connected to said first reset input terminal of said first R-S flip-flop, whereby the output of said analog memory may be controlled by the operations of said down, up and stop switches.
Claim 2
Dependent Claim
172 words
A DC voltage control device comprising (a) an analog memory comprising a MOS field-effect transistor, and a nonpolarized capacitor (b) a first R-S flip-flop connected to a first input terminal of said analog memory, (c) a second R-S flip-flop connected to a second input terminal of said analog memory, (d) a first diode connected between a second set input terminal of said second R-S flip-flop and a first set input terminal of said first R-S flip-flop, (e) a second diode connected between a second rest input terminal of said second R-S flip-flop and a first set input terminal of said first R-S flip-flop, (f) a down switch connected to said second set input terminal of said second R-S flip-flop, (g) an up switch connected to said second reset input terminal of said second R-S flip-flop, and (h) a stop switch connected to said first reset input terminal of said first R-S flip-flop, whereby the output of said analog memory may be controlled by the operations of said down, up and stop switches.
Claim 3
Dependent Claim
24 words
A DC voltage control device as set forth in claim 1 wherein an analog switch in said analog memory consists of a reed relay.
Claim 4
Dependent Claim
24 words
A DC voltage control device as set forth in claim 1 wherein an analog switch in said analog memory consists of a semiconductor switch.
Claim 5
Dependent Claim
62 words
A DC voltage control device as set forth in claim 1 wherein the output terminal of said analog memory is connected to the input terminals of an upper limit setting circuit and a lower limit setting circuit, and the output terminals of said upper and lower limit setting circuits are connected to said first reset input terminal of said first R-S flip-flop.
Claim 6
Dependent Claim
23 words
A DC voltage control device as set forth in claim 4 wherein said upper and lower limit setting circuits consist of operational amplifiers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |