Semiconductor device and a logical circuit formed of the same

Claim 2

A semiconductor device comprising: a plurality of depletion-type MOS transistors having source, drain and channel regions and at least one enhancement-type MOS transistor having source and drains regions formed of the channel regions of the depletion-type MOS transistor and a channel region.

Claim 3

A semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a plurality of first regions formed in matrix arrangement on said semiconductor substrate and having a second-conductivity-type opposite to that of said substrate; a plurality of second-conductivity-type second regions formed on first portions of said semiconductor substrate between said first regions along the rows of the matrix arrangement of said second-conductivity-type first regions and arranged in the shape of a matrix; a plurality of gate insulating films formed, along the columns of the matrix arrangement of said second regions, on said second regions and second portions of said semiconductor substrate which are positioned between said second regions along the columns of the matrix arrangement, said gate insulating films having thick portions which are selectively formed on said second portions of said semiconductor substrate; and a plurality of conductive films respectively formed on said gate insulating films; said first regions and said second regions alternately disposed along said line composing at least one depletion-type MOS transistor, and said second regions and said second portions of the semiconductor substrate alternately disposed along said column composing at least one enhancement-type MOS transistor, said second regions functioning as a source and a drain of said enhancement-type MOS transistor as well as a channel of said depletion-type MOS transistor.

Claim 4

A semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a plurality of first regions formed in matrix arrangement on said semiconductor substrate and having a second-conductivity-type opposite to that of said substrate; a plurality of second-conductivity-type second regions formed on first portions of said semiconductor substrate between said first regions along the rows of the matrix arrangement of said second-conductivity-type first regions and arranged in the shape of a matrix; a plurality of gate insulating films formed, along the columns of the matrix arrangement of said second regions, on said second regions and second portions of said semiconductor substrate which are positioned between said second regions along the columns of the matrix arrangement, said gate insulating films having thick portions which are selectively formed on said second portions of said semiconductor substrate; and a plurality of conductive films respectively formed on said gate insulating films; said first regions and said second regions alternately disposed along said line composing at least one depletion-type MOS transistor, and said second regions and said second portions of the semiconductor substrate alternately disposed along said column composing at least one enhancement-type MOS transistor, said second regions functioning as a source and a drain of said enhancement-type MOS transistor as well as a channel of said depletion-type MOS transistor.

Claim 5

A semiconductor device according to claim 1, wherein said second-conductivity-type first regions include at least first and second first-regions formed along a first row of the matrix arrangement and at least first and second first-regions formed along a second row of the matrix arrangement, said second-conductivity-type second-regions include first second-region formed between said first and second first-regions along said first row and second-region formed between said first and second first-region along said second row, said first and second first-regions along said first row and said first second-region compose a depletion-type MOS transistor, and said first and second second-regions and said second portion of the substrate between said first and second second-regions compose an enhancement-type MOS transistor.

Claim 6

A semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a plurality of first regions formed in matrix arrangement on said semiconductor substrate and having a second-conductivity-type opposite to that of said substrate; a plurality of second-conductivity-type second regions formed on first portions of said semiconductor substrate between said first regions along the a plurality of rows of the matrix arrangement of said second-conductivity-type first regions and arranged in the shape of a matrix; a plurality of gate insulating films formed, along a plurality of columns of the matrix arrangement of said second regions, on said regions and second portions of said semiconductor substrate which are positioned between said second regions along the columns of the matrix arrangement, said gate insulating films having thick portions which are selectively formed on said second portions of said semiconductor substrate; and a plurality of conductive films respectively formed on said gate insulating films; said first regions and said second regions alternately disposed along said line compositing a plurality of depletion-type MOS transistors, and said second regions and said second portions of the semiconductor substrate alternately disposed along said column composing a plurality of enhancement-type MOS transistors, said second regions functioning as sources and drains of said enhancement-type MOS transistors as well as channels of said depletion-type MOS transistors.

Claim 7

A semiconductor device, comprising: a first-conductivity-type semiconductor substrate; a plurality of first regions formed in matrix arrangement on said semiconductor substrate and having a second-conductivity-type opposite to that of said substrate; a plurality of second-conductivity-type second regions formed on first portions of said semiconductor substrate between said first regions along the a plurality of rows of the matrix arrangement of said second-conductivity-type first regions and arranged in the shape of a matrix; a plurality of gate insulating films formed, along a plurality of columns of the matrix arrangement of said second regions, on said regions and second portions of said semiconductor substrate which are positioned between said second regions along the columns of the matrix arrangement, said gate insulating films having thick portions which are selectively formed on said second portions of said semiconductor substrate; and a plurality of conductive films respectively formed on said gate insulating films; said first regions and said second regions alternately disposed along said line compositing a plurality of depletion-type MOS transistors, and said second regions and said second portions of the semiconductor substrate alternately disposed along said column composing a plurality of enhancement-type MOS transistors, said second regions functioning as sources and drains of said enhancement-type MOS transistors as well as channels of said depletion-type MOS transistors.

Claim 8

A semiconductor device according to claim 4, wherein said gate insulating films are formed of SiO 2 .

Claim 9

A semiconductor device according to claim 4, wherein said conductive films are formed of polycrystalline silicon.

Claim 10

A semiconductor device according to claim 4, wherein a protective film is formed over the surface of said semiconductor device.

Claim 11

A semiconductor device according to claim 4, wherein said semiconductor substrate is formed of a P-type silicon substrate, and said first and second regions contain an N-type impurity.

Claim 12

A semiconductor device according to claim 4, wherein said gate insulating films include thin insulating films 500 to 1,200A thick including selectively thick insulating portions 8,000 to 15,000A.

Claim 13

A logical circuit, comprising: a first transistor series circuit composed of a plurality of first depletion-type MOS transistors having channel regions and formed in series in a first line direction on a semiconductor substrate; a second transistor series circuit composed of a plurality of second depletion-type MOS transistors having channel regions and formed in series in a second line direction on said semiconductor substrate; a plurality of enhancement-type MOS transistors having sources and drains thereof formed of the respective channel regions of said first depletion-type MOS transistors in said first series circuit and the respective channel regions of said second depletion-type MOS transistors in said second series circuit, respectively, for selectively connecting said first MOS transistors in said first transistor series circuit with said second MOS transistors in said second transistor series circuit; and a plurality of input lines for supplying address signals respectively to a plurality of transistor groups each composed of each corresponding ones among said first and second depression-type transistors and said enhancement-type transistors.

Claim 14

A logical circuit, comprising: a first transistor series circuit composed of a plurality of first depletion-type MOS transistors having channel regions and formed in series in a first line direction on a semiconductor substrate; a second transistor series circuit composed of a plurality of second depletion-type MOS transistors having channel regions and formed in series in a second line direction on said semiconductor substrate; a plurality of enhancement-type MOS transistors having sources and drains thereof formed of the respective channel regions of said first depletion-type MOS transistors in said first series circuit and the respective channel regions of said second depletion-type MOS transistors in said second series circuit, respectively, for selectively connecting said first MOS transistors in said first transistor series circuit with said second MOS transistors in said second transistor series circuit; and a plurality of input lines for supplying address signals respectively to a plurality of transistor groups each composed of each corresponding ones among said first and second depression-type transistors and said enhancement-type transistors.

Claim 15

A logical circuit according to claim 10 which comprise a plurality of logical circuit blocks each composed of said first series circuit, said second series circuit, and a plurality of said enhancement-type MOS transistors for connecting said first and second series circuits.