Patent US4143178A successfully refreshed from Google Patents.
US4143178A
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US
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Manufacturing method of semiconductor devices
Assignee: Toshiba Corp
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Filing: 1977-07-07
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Granted: 1979-03-06
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Expires: 1997-07-07
Abstract
Abstract A manufacturing method of semiconductor device having a single layer or multilayer of polycrystalline semiconductor including doped impurity is provided which comprises a step of forming a first polycrystalline semiconductor layer with doped impurity on a semiconductor substrate and another step of forming a second polycrystalline semiconductor layer without doped impurity on the first polycrystalline semiconductor layer. The manufacturing method of the invention provides excellent MOS FET's in the semiconductor device of which the threshold voltage varies little. High reliable semiconductor device may further be manufactured with a high yield.
Inventors
- 👤 Nozomu Harada
- 👤 Nobuhisa Kubota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:17
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10B; H10B12/00; H10B12/30; H10B69/00; H10P; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; Y; Y10; Y10S; Y10S148/00; Y10S148/025; Y10S148/051; Y10S148/053; Y10S148/117; Y10S148/122
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
99 words
A manufacturing method of semiconductor devices having polycrystalline semiconductor layer doped with impurity, comprising the steps of: forming a first polycrystalline semiconductor layer doped with impurity on a substrate; forming a second polycrystalline semiconductor layer undoped with impurity on said first polycrystalline semiconductor layer; removing selectively said first and second polycrystalline semiconductor layers from the substrate to expose portions of the substrate; and thermal-oxidizing the second polycrystalline semiconductor layer undoped with impurity and some exposed portions of the substrate, the impurities in the first polycrystalline semiconductor layer being diffused into the second polycrystalline semiconductor layer during the thermal-oxidizing step.
Claim 2
Dependent Claim
99 words
A manufacturing method of semiconductor devices having polycrystalline semiconductor layer doped with impurity, comprising the steps of: forming a first polycrystalline semiconductor layer doped with impurity on a substrate; forming a second polycrystalline semiconductor layer undoped with impurity on said first polycrystalline semiconductor layer; removing selectively said first and second polycrystalline semiconductor layers from the substrate to expose portions of the substrate; and thermal-oxidizing the second polycrystalline semiconductor layer undoped with impurity and some exposed portions of the substrate, the impurities in the first polycrystalline semiconductor layer being diffused into the second polycrystalline semiconductor layer during the thermal-oxidizing step.
Claim 3
Dependent Claim
45 words
A manufacturing method of semiconductor devices according to claim 1, in which said first polycrystalline semiconductor is formed by CVD method supplying impurity to a reactor system, and said second polycrystalline semiconductor layer is formed by CVD method supplying no impurity to the reactor system.
Claim 4
Dependent Claim
32 words
A manufacturing method of semiconductor devices according to claim 1, in which said first polycrystalline semiconductor layer is formed by doping impurity into said polycrystalline layer undoped with impurity, through thermal diffusion.
Claim 5
Dependent Claim
33 words
A manufacturing method of semiconductor devices according to claim 1, in which said first and second polycrystalline semiconductor layers are each formed by controllingly ion-injection impurity the polycrystalline semiconductor layer undoped with impurity.
Claim 6
Dependent Claim
17 words
A manufacturing method of semiconductor devices according to claim 1, in which said polycrystalline semiconductor is polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-05 | 1982-09-04 | 1983-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-05 | 1986-09-04 | 1987-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-05 | 1990-09-04 | 1991-03-06 | $7700.00 | Window Closed / Lapsed |