Multi-frequency digital wave synthesizer for providing analog output signals

Claim 2

A multi-frequency digital wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment; (d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and (e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals.

Claim 3

The synthesizer of claim 1 wherein the segment period determining means comprises a counter, responsive to the binary representation, activated by electrical pulses from the system clock, to count a number of the electrical pulses corresponding to the binary representation thereby providing the real time period.

Claim 4

The synthesizer of claim 2 wherein the counter is a decrementing counter, originally loaded from the logic array means with the binary representation, that provides an indicia pulse to the segment counting means when the count of the binary representation has been completed thereby indicating that a segment has been completed.

Claim 5

The synthesizer of claim 1 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequencies desired; and (ii) address register means, responsive to the address register select means and to the segment selecting means for addressing the logic array means.

Claim 6

The synthesizer of claim 2 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequencies desired; and (ii) address register means, responsive to the address register select means and to the segment selecting means for addressing the logic array means.

Claim 7

The synthesizer of claim 1 wherein the segment selecting means comprises a counter for sequentially counting the occurrence of the segments.

Claim 8

The synthesizer of claim 2 wherein the segment selecting means further comprises a counter for sequentially counting the segments.

Claim 9

The synthesizer of claim 4 wherein the segment selecting means comprises a counter for sequentially counting the occurrence of the segments.

Claim 10

The synthesizer of claim 5 wherein the segment selecting means further comprises a counter for sequentially counting the occurrence of the segments.

Claim 11

The synthesizer of claim 1 wherein the wave generator means further comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 12

The synthesizer of claim 2 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 13

The synthesizer of claim 5 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 14

The synthesizer of claim 7 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 15

The synthesizer of claim 9 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 16

The synthesizer of claim 1 wherein the logic array comprises a programmable logic array (PLA).

Claim 17

The synthesizer of claim 15 wherein the logic array means further comprises a read-only-memory (ROM).

Claim 18

The synthesizer of claim 14 wherein the logic array comprises a programmable logic array (PLA).

Claim 19

The synthesizer of claim 17 wherein the logic array means further comprises a read-only-memory (ROM).

Claim 20

An electronic multi-frequency digital wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an interger greater than one, in response to a corresponding electrical digital signal input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals equals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output of the segment counting means for identifying the segment and to the output of the segment period determining means for providing successively n/2 predetermined voltages each corresponding to a selected segment for the duration (A and B) of the segment period for each of the n segments.

Claim 21

An electronic multi-frequency digital wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an interger greater than one, in response to a corresponding electrical digital signal input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals equals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output of the segment counting means for identifying the segment and to the output of the segment period determining means for providing successively n/2 predetermined voltages each corresponding to a selected segment for the duration (A and B) of the segment period for each of the n segments.

Claim 22

The synthesizer of claim 19 wherein B = A+1, in microseconds.

Claim 23

The synthesizer of claim 20 wherein x+y = n = 16.

Claim 24

The synthesizer of claim 19 wherein the segment period determining means comprises a counter, responsive to the binary representation, activated by electrical pulses from the system clock to count a number of electrical pulses to provide the real time period corresponding to the binary representation of A and B.

Claim 25

The synthesizer of claim 22 wherein the counter is a decrementing counter, originally loaded from the logic array means with the binary representation, that provides an indicia pluse to the segment counting means when the count of the binary representation has been completed thereby indicating that a segment has been completed.

Claim 26

The synthesizer of claim 19 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequencies desired; and (ii) address register means, responsive to the address register select means and to the segment counting means for addressing the logic array means.

Claim 27

The synthesizer of claim 22 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequencies desired; and (ii) address register means, responsive to the address register select means and to the segment counting means for addressing the logic array means.

Claim 28

The synthesizer of claim 19 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment counting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 29

The synthesizer of claim 22 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment counting means, each stage of the register being connected to the second terminal of the respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 30

The synthesizer of claim 24 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference source; and (iii) a register, selectively loadable from the segment counting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 31

The synthesizer of claim 25 wherein the wave generator means comprises: (e) (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference source; and (iii) a register, selectively loadable from the segment counting means, each stage of the register being connected to the second terminal of a respective one of the plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 32

The synthesizer of claim 19 wherein the logic array means comprises a programmable logic array (PLA).

Claim 33

The synthesizer of claim 30 wherein the logic array means further comprises a read-only-memory (ROM).

Claim 34

The synthesizer of claim 21 wherein the logic array means comprises a programmable logic array (PLA).

Claim 35

The synthesizer of claim 32 wherein the logic array means further comprises a read-only-memory (ROM).

Claim 36

In a multi-frequency digital wave synthesizer for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, the method of providing an analog output signal comprising the steps of: (a) storing in logic array means the binary representation of the periods of the n successive segments for all of the plurality of analog output signals; (b) addressing the logic array means including inputting the digital signal input to provide the binary representation of the addressed segment; (c) changing the binary representation provided from the logic array means to the segment period in real time by counting a counter using a fixed frequency; (d) selecting a voltage level and providing that level as an output during the segment period to form one of the plurality of analog output signals; (e) counting the segments and providing the next count to the logic array means to address the next sequential segment; and (f) repeating steps b through e until the waveform has been completed.

Claim 37

In a multi-frequency digital wave synthesizer for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, the method of providing an analog output signal comprising the steps of: (a) storing in logic array means the binary representation of the periods of the n successive segments for all of the plurality of analog output signals; (b) addressing the logic array means including inputting the digital signal input to provide the binary representation of the addressed segment; (c) changing the binary representation provided from the logic array means to the segment period in real time by counting a counter using a fixed frequency; (d) selecting a voltage level and providing that level as an output during the segment period to form one of the plurality of analog output signals; (e) counting the segments and providing the next count to the logic array means to address the next sequential segment; and (f) repeating steps b through e until the waveform has been completed.

Claim 38

The method of claim 34 including the following additional steps after step (e); (g) addressing a different segment in response to a change in the input digital signal; (h) maintaining the sequence of the segment count.

Claim 39

A multi-frequency digital sine wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment; (d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and (e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising: (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 40

A multi-frequency digital sine wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment; (d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and (e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising: (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 41

The synthesizer of claim 36 wherein the segment period determining means comprises a counter, responsive to the binary representation, activated by electrical pulses from the system clock, to count a number of the electrical pulses corresponding to the binary representation thereby providing the real time period.

Claim 42

The synthesizer of claim 37 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequency desired; and (ii) address register means, responsive to the address register select means and to the segment selecting means for addressing the logic array means.

Claim 43

The synthesizer of claim 37 wherein the segment selecting means comprises a counter for sequentially counting the occurrence of the segments.

Claim 44

The synthesizer of claim 38 wherein the segment selecting means comprises a counter for sequentially counting the occurrence of the segments.

Claim 45

The synthesizer of claim 40 wherein the logic array means comprises a programmable logic array (PLA).

Claim 46

The synthesizer of claim 41 wherein the logic array means further comprises a read-only-memory (ROM).

Claim 47

An electronic multi-frequency digital sine wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one in response to a corresponding electrical digital input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment and to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means in response to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising: (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 48

An electronic multi-frequency digital sine wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one in response to a corresponding electrical digital input, comprising: (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment and to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means in response to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising: (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded.

Claim 49

The synthesizer of claim 43 wherein the segment period determining means comprises a counter, responsive to the binary representation, activated by electrical pulses from the system clock, to count a number of the electrical pulses corresponding to the binary representation thereby providing the real time period.

Claim 50

The synthesizer of claim 43 wherein the addressing means comprises: (b) (i) address register select means having inputs for selecting the output frequency desired; and (ii) address register means, responsive to the address select means and to the segment selecting means for addressing the logic array means.

Claim 51

The synthesizer of claim 44 wherein the segment period determining means comprises a counter, responsive to the binary representation, activated by electrical pulses from the system clock, to count a number of electrical pulses corresponding to the binary representation thereby providing the real time period.