Floppy disc data separator for use with single density encoding

Claim 2

A circuit for separating data from a data encoded signal consisting of clock pulses and data positioned therebetween, comprising: data window means for generating as outputs a data window signal and the inverse thereof, said data window means having an input for receiving said clock pulses and including means or automatically adjusting the timing of said data window signal in response to changes in the timing of said clock pulses, whereby said data window signal is continuously maintained in a predetermined time relationship to said clock pulses, input gate means connected to an output of said data window means for receiving said data encoded signal and gating only said clock pulses to said data window means input, and gating means for separating said data from said clock pulses, comprising a gate circuit and connecting means connecting said data encoded signal and said data window signal thereto.

Claim 3

The circuit as described in claim 1, wherein said data encoded signal is a single density encoded signal, said data window signal is periodically high coincident with the data in said signal and periodically low coincident with said clock pulses, and said gate circuit comprises an and gate.

Claim 4

The circuit as described in claim 1, wherein said data window means comprises a phase locked loop circuit for providing a signal output which is aligned with said clock pulses.

Claim 5

The circuit as described in claim 3, comprising sector lock means for resetting said circuit upon receipt of a signal representing the start of a floppy disc sector.

Claim 6

A circuit for separating data and clock signals from a single density encoded signal, comprising: a phase locked loop circuit, having two inputs, and providing a pulse oscillator output; first logic means for producing a first logic signal in time alignment with said oscillator output, having an input connected to receive said oscillator output, and a connecting circuit for connecting said first logic signal to one of said phase locked loop circuit inputs; second logic means having an input connected to receive said oscillator output, for generating second and third logic signals in time alignment with said oscillator output; first gate circuit means for providing separated clock signals having a first input connected to receive said single density encoded signal and a second input connected to receive said third logic signal, and an output connected to a second input of said phase locked loop circuit at which is provided the separated clock signals; and second gate circuit means for providing separated data signals having a first input connected to receive said single density encoded signal and a second input connected to receive said second logic signal, and an output terminal at which is provided the separated data signals derived from said encoded signal.

Claim 7

A circuit for separating data and clock signals from a single density encoded signal, comprising: a phase locked loop circuit, having two inputs, and providing a pulse oscillator output; first logic means for producing a first logic signal in time alignment with said oscillator output, having an input connected to receive said oscillator output, and a connecting circuit for connecting said first logic signal to one of said phase locked loop circuit inputs; second logic means having an input connected to receive said oscillator output, for generating second and third logic signals in time alignment with said oscillator output; first gate circuit means for providing separated clock signals having a first input connected to receive said single density encoded signal and a second input connected to receive said third logic signal, and an output connected to a second input of said phase locked loop circuit at which is provided the separated clock signals; and second gate circuit means for providing separated data signals having a first input connected to receive said single density encoded signal and a second input connected to receive said second logic signal, and an output terminal at which is provided the separated data signals derived from said encoded signal.

Claim 8

The circuit as described in claim 5, wherein said first logic means comprises a first divide-by-two flip-flop, and said second logic means comprises an inverter circuit connected to the clock input of a second divide-by-two flip-flop.

Claim 9

The circuit as described in claim 6, wherein said flip-flops are D-type flip-flops, and the D terminals are connected in common.

Claim 10

The circuit as described in claim 5, wherein said second logic signal is in time coincidence with the data signals in said encoded signal and said third logic signal is in time coincidence with the clock signals in said encoded signal.

Claim 11

The circuit as described in claim 8, wherein said phase locked loop circuit keeps said pulse oscillator output in edge alignment with said clock signals.

Claim 14

The circuit as described in claim 1, comprising second gating means for separating said clock pulses from said encoded signal.