Missing clock detection circuit

Claim 2

In a data processing system wherein data bits and clock bits are serially and alternately encoded, a missing clock pulse detector comprising: input means for receiving said data bits and said clock bits; first means coupled to said input means for establishing a first time period of greater duration than the interval between succeeding clock and data bits and of less duration than the interval between said succeeding clock bits having a data bit interposed therebetween; second means coupled to said input means for establishing a second time period of greater duration than the interval between said succeeding clock bits and of less duration than the interval between the first of said succeeding clock bits and the data bit adjacent to the second of said succeeding clock bits; means including said second means for detecting the occurrence of a missing clock bit; and means responsive to the detection of a missing clock bit for decoding the next bit following the missing clock bit as either a data bit or a clock bit depending upon whether said next bit is detected within said first or said second time period.

Claim 3

In a data processing system in accordance with claim 1, a missing clock pulse detector further comprising means coupled to said means for decoding the next bit following the missing clock bit for inserting one or more predetermined data bits into at least the next position in time adjacent to the position of said missing clock bit.

Claim 4

In a data processing system in accordance with claim 2, a missing clock pulse detector wherein said inserted predetermined data bits comprises a one-bit correction code.

Claim 5

In a data processing system in accordance with claim 2, a missing clock pulse detector wherein said inserted predetermined data bits comprises a multi-bit correction code.

Claim 6

In a data processing system in accordance with claim 1, a missing clock pulse detector wherein said means for decoding the next bit following the missing clock bit includes means for determining whether said next bit is received before or after said first period such that said next bit is decoded as a clock bit when said missing clock is detected and said second period has elapsed.

Claim 7

In a data processing system in accordance with claim 1, a missing clock pulse detector wherein said first time period is indicative of the time following the detection of each clock bit and wherein said next bit received within said first time period after receiving said clock bit is decoded as a data bit and a bit received after the end of said first time period is decoded as a clock bit; and wherein said second time period is indicative of the time duration after each clock bit is received such that a missing clock bit is indicated when the next clock bit is not received within said second period.

Claim 8

In a data processing system in accordance with claim 1, a missing clock pulse detector wherein said means for establishing said first time period and said means for establishing said second time period comprise first and second timer circuits respectively.

Claim 9

In a data processing system in accordance with claim 1, a missing clock pulse detector wherein said alternately encoded clock and data bits are encoded on a magnetic media.

Claim 10

In a data processing system in accordance with claim 1, a missing clock pulse detector wherein said means for detecting a missing clock comprises a timer circuit for generating a pulse upon the detection of a missing clock bit.

Claim 11

A missing clock pulse detection circuit for detecting the non-occurrence of a clock bit in a serial bit-stream of alternately encoded clock and data bits comprising: first and second AND gates each having a pair of input terminals, said bit-stream being coupled to one of said input terminals of each of said AND gates; a first timer circuit having a period longer than the interval between succeeding clock and data bits and shorter than the interval between succeeding clock bits with a data bit interposed therebetween; a first flip-flop having an inverted output coupled to the other input terminal of said first AND gate and a noninverted output coupled to the other input terminal of said second AND gate, and having an input corresponding to the output of said first AND gate, said first AND gate output also being coupled to the set input of said first timer circuit, the output of said first timer circuit being coupled to the reset terminal of said first flip-flop; a second timer circuit having a second period which is the same as the period of said first timer circuit, and having an input corresponding to the output of the second AND gate, and wherein said second timer circuit has at least one output coupled therefrom; and a second flip-flop having the output of said second timer circuit coupled to the data input thereof and the output of said first AND gate coupled to the clock input of said second flip-flop, and wherein said second flip-flop has a data output.

Claim 12

A missing clock pulse detection circuit for detecting the non-occurrence of a clock bit in a serial bit-stream of alternately encoded clock and data bits comprising: first and second AND gates each having a pair of input terminals, said bit-stream being coupled to one of said input terminals of each of said AND gates; a first timer circuit having a period longer than the interval between succeeding clock and data bits and shorter than the interval between succeeding clock bits with a data bit interposed therebetween; a first flip-flop having an inverted output coupled to the other input terminal of said first AND gate and a noninverted output coupled to the other input terminal of said second AND gate, and having an input corresponding to the output of said first AND gate, said first AND gate output also being coupled to the set input of said first timer circuit, the output of said first timer circuit being coupled to the reset terminal of said first flip-flop; a second timer circuit having a second period which is the same as the period of said first timer circuit, and having an input corresponding to the output of the second AND gate, and wherein said second timer circuit has at least one output coupled therefrom; and a second flip-flop having the output of said second timer circuit coupled to the data input thereof and the output of said first AND gate coupled to the clock input of said second flip-flop, and wherein said second flip-flop has a data output.

Claim 13

A missing clock pulse detection circuit in accordance with claim 10 further comprising: a missing clock detection timer circuit having as the input thereof the clock input to said second flip-flop, and an output indicative of the detection of a missing clock pulse.

Claim 14

A missing clock pulse detection circuit in accordance with claim 11 further comprising: means coupled to said data output of said second flip-flop, said first and second AND gate outputs and said output of said missing clock detection timer circuit for inserting an error correction code into the bit stream immediately adjacent in time to the detected missing clock bit location.

Claim 15

A missing clock detector comprising: a source of serially and alternately encoded clock and data bits; means for detecting said clock and data bits, including means for detecting the occurrence of one or more missing clock bits comprising a first timer circuit for detecting a first time period of greater duration than the time period between succeeding clock and data bits and less duration than the timer period between succeeding clock bits having a data bit interposed therebetween; a second timer circuit for detecting a second time preiod of greater duration than the time period between two succeeding clock bits and of less duration than the time period between one clock and data bit adjacent to the immediate succeeding clock bit; and means responsive to said first and second timer circuits for decoding the next bit following the missing clock as either a data bit or a clock bit.

Claim 16

A missing clock detector comprising: a source of serially and alternately encoded clock and data bits; means for detecting said clock and data bits, including means for detecting the occurrence of one or more missing clock bits comprising a first timer circuit for detecting a first time period of greater duration than the time period between succeeding clock and data bits and less duration than the timer period between succeeding clock bits having a data bit interposed therebetween; a second timer circuit for detecting a second time preiod of greater duration than the time period between two succeeding clock bits and of less duration than the time period between one clock and data bit adjacent to the immediate succeeding clock bit; and means responsive to said first and second timer circuits for decoding the next bit following the missing clock as either a data bit or a clock bit.

Claim 17

A missing clock detector in accordance with claim 13 wherein said decoding means comprises a logic circuit for determining whether said next bit is received before or after said first period such that said next bit is decoded as a clock bit when said missing clock is detected and when said second period has elapsed.

Claim 18

A missing clock detector in accordance with claim 13 further comprising means coupled to said means for decoding and to said second timer circuit responsive to the detection of the missing clock bit for inserting a predetermined correction code into the next position in time adjacent to the position of the said missing clock bit.

Claim 19

A missing clock detector in accordance with claim 13 wherein said first timer circuit measures the time following the detection of each clock bit, such that the next bit received within said first period after the clock bit, is decoded as a data bit and a bit received after the end of said first period is decoded as a clock bit; and said second timer circuit measures the time after each clock bit and decodes a missing clock bit as having occurred when the next clock bit is not detected within said second period.

Claim 20

A missing clock detector comprising: a source of serially and alternating encoded clock and data bits; means for detecting said clock and data bits; means reponsive to said detecting means for detecting one or more missing clock bits including, means for establishing a first time period of greater duration than the interval between succeeding clock and data bits and of less duration than the interval between succeeding clock bits having a data bit interposed therebetween; means for establishing a second time period of greater duration than the interval between succeeding clock bits and of less duration that the interval between one of said clock bits and a data bit adjacent to the immediately following clock bit; and logic means responsive to the detection of said missing clock bit for decoding the next bit following the missing clock as a data bit or clock bit in accordance with the decoding of said next bit in either said first or said second time period.

Claim 21

A missing clock detector comprising: a source of serially and alternating encoded clock and data bits; means for detecting said clock and data bits; means reponsive to said detecting means for detecting one or more missing clock bits including, means for establishing a first time period of greater duration than the interval between succeeding clock and data bits and of less duration than the interval between succeeding clock bits having a data bit interposed therebetween; means for establishing a second time period of greater duration than the interval between succeeding clock bits and of less duration that the interval between one of said clock bits and a data bit adjacent to the immediately following clock bit; and logic means responsive to the detection of said missing clock bit for decoding the next bit following the missing clock as a data bit or clock bit in accordance with the decoding of said next bit in either said first or said second time period.

Claim 22

A missing clock detector in accordance with claim 17, further comprising: means for correcting the decoding of a data bit as a clock bit upon the occurrence of the next clock bit following the missing of said clock bit occurrence when said data bit immediately following the occurrence of said missing clock bit is decoded as a clock bit.

Claim 23

A signal processing circuit for decoding a signal waveform containing clock signals interleaved with data signals comprising: input means for receiving said signal waveform; first and second gates, with said input means including means for applying said signal waveform to an input of each of said first and second gates, and with said first gate having an output coupled to a utilization circuit; first and second timers, with said second gate having an output coupled to said first and said second timers, said first timer having a pair of complementary outputs coupled respectively to said first gate and said second gate, said first timer being operable to reverse signals present on said complementary outputs for a first predetermined time period in response to a signal on the output of said second gate, said second timer being operable to provide an output signal in response to the time interval between successive signals on the output of said second gate being greater than a second predetermined time period, said signal processing circuit being operable whereby each clock signal is effective to cause a signal to appear on the output of said second gate, and said second timer is effective to provide an output indication signal in the event of a clock signal being missing from between two adjacent data signals.

Claim 24

A signal processing circuit for decoding a signal waveform containing clock signals interleaved with data signals comprising: input means for receiving said signal waveform; first and second gates, with said input means including means for applying said signal waveform to an input of each of said first and second gates, and with said first gate having an output coupled to a utilization circuit; first and second timers, with said second gate having an output coupled to said first and said second timers, said first timer having a pair of complementary outputs coupled respectively to said first gate and said second gate, said first timer being operable to reverse signals present on said complementary outputs for a first predetermined time period in response to a signal on the output of said second gate, said second timer being operable to provide an output signal in response to the time interval between successive signals on the output of said second gate being greater than a second predetermined time period, said signal processing circuit being operable whereby each clock signal is effective to cause a signal to appear on the output of said second gate, and said second timer is effective to provide an output indication signal in the event of a clock signal being missing from between two adjacent data signals.

Claim 25

A signal processing circuit in accordance with claim 19, wherein said first timer includes a flip-flop having true and false outputs coupled to said first and second gates respectively, and a timer circuit, a signal appearing on the output of said second gate being effective to set said flip-flop from a first to a second state, and to initiate operation of said timer circuit, said flip-flop being reset from said second to said first state after said first predetermined time period has elapsed.

Claim 26

A signal processing circuit in accordance with claim 20, wherein said second timer includes a timing circuit operable to be set from a first to a second state in response to a signal on the output of said second gate and to be reset from said second to said first state in the absence of a signal on the output of said second gate during said second predetermined time period, thereby providing said output indication signal on an output of said timing circuit.

Claim 27

A signal processing circuit in accordance with claim 19, wherein said clock signals are in the form of clock pulses, wherein said data signals are in the form of the presence or absence of a data pulse, and wherein said signal waveform includes a data location signal including the absence of a clock pulse at a clock pulse time followed by the presence of a data pulse, which data pulse is effective to cause a signal to appear on the output of said second gate.

Claim 28

A signal processing circuit in accordance with claim 22, wherein said data location signal further includes the absence of a clock pulse at a further clock pulse time followed by the absence of a data pulse, whereby the clock pulse at the clock pulse time next after said further clock pulse time is effective to cause a signal to appear on the output of said second gate.