Patent FR708098A successfully refreshed from Google Patents.
US4140922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier stage for the current supply of I2 L circuits
Assignee: Siemens AG
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Filing: 1977-05-26
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Granted: 1979-02-20
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Expires: 1997-05-26
Abstract
Abstract An amplifier stage is provided for supplying differing currents to integrated injection logic I 2 L circuits. The amplifier stage has a current hogging injection logic input CHIL gate, at least one further gate, and a CHIL output gate. Each of the gates has an injecting emitter, an output and an input. First I 2 L circuits connected to a first injector path connect with the input of the CHIL input gate. Second I 2 L circuits having a second injector path connect with an output of the CHIL output gate. The gate provided between the input and output CHIL gates is provided as a single I 2 L gate, dual I 2 L gates, or the combination of an I 2 L gate and a CHIL gate.
Inventors
- 👤 Ruediger Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01818
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
283 words
An amplifier stage for supplying integrated injection logic (I 2 L) circuit with differing currents, said I 2 L circuits including a first I 2 L circuit having a first transistor with an injecting emitter and connected via said injecting emitter to a first injector path, a further I 2 L circuit having a first transistor with an injecting emitter connected via said injecting emitter to a further injector path, and differing currents flowing in the first and further injector paths, wherein said amplifier stage comprises: a current hogging injection logic (CHIL) input gate having a transistor with an injecting emitter, an output, and an input; at least one gate having a transistor with an injecting emitter, an output, and an input, a CHIL output gate having a transistor with an injecting emitter, an output, and an input; the CHIL input gate input being connected to an output of the first I 2 L circuit and the CHIL output gate output being connected to an input of the further I 2 L circuit; the CHIL input gate and said at least one gate being connected by their injecting emitters to the first injector path; the CHIL output gate injecting emitter being connected to the further injector path and by its input coupled to the first injector path; the CHIL input gate output being connected to the input of the at least one gate; amd the at least one gate output being conneced to the input of the CHIL output gate; whereby the current at the output of the first I 2 L circuit is amplified in stepped fashion via the CHIL input gate, the at least one gate, and the CHIL output gate.
Claim 2
Dependent Claim
283 words
An amplifier stage for supplying integrated injection logic (I 2 L) circuit with differing currents, said I 2 L circuits including a first I 2 L circuit having a first transistor with an injecting emitter and connected via said injecting emitter to a first injector path, a further I 2 L circuit having a first transistor with an injecting emitter connected via said injecting emitter to a further injector path, and differing currents flowing in the first and further injector paths, wherein said amplifier stage comprises: a current hogging injection logic (CHIL) input gate having a transistor with an injecting emitter, an output, and an input; at least one gate having a transistor with an injecting emitter, an output, and an input, a CHIL output gate having a transistor with an injecting emitter, an output, and an input; the CHIL input gate input being connected to an output of the first I 2 L circuit and the CHIL output gate output being connected to an input of the further I 2 L circuit; the CHIL input gate and said at least one gate being connected by their injecting emitters to the first injector path; the CHIL output gate injecting emitter being connected to the further injector path and by its input coupled to the first injector path; the CHIL input gate output being connected to the input of the at least one gate; amd the at least one gate output being conneced to the input of the CHIL output gate; whereby the current at the output of the first I 2 L circuit is amplified in stepped fashion via the CHIL input gate, the at least one gate, and the CHIL output gate.
Claim 3
Dependent Claim
24 words
An amplifier stage as claimed in claim 1, characterized in that the at last one gate comprises at least one I 2 L gate.
Claim 4
Dependent Claim
47 words
An amplifier stage as claimed in claim 1, characterized in that the at least one gate comprises at least one CHIL gate having an output and at least one I 2 L gate having an input connecting to the output of the at least one CHIL gate.
Claim 5
Dependent Claim
51 words
An amplifier stage as claimed in claim 1, characterized in that the CHIL input gate and the CHIL output gate each comprise a lateral pnp transistor and a vertical npn transistor, a collector of the lateral transistor connecting to a base of the vertical transistor and to the respective circuit input.
Claim 6
Dependent Claim
49 words
An amplifier as claimed in claim 1, characterized in that the first and further I 2 L circuits consist of a lateral pnp transistor and a vertical npn transistor, a collector of the lateral transistor connecting to a base of the vertical transistor and to the respective circuit input.
Claim 7
Dependent Claim
47 words
An amplifier stage as claimed in claim 1, characterized in that the stage is arranged in a n + doped silicon layer and a n conducting epitaxial layer arranged on the silicon layer, the epitaxial layer being divided into individual troughs in which the gates are arranged.
Claim 8
Dependent Claim
58 words
Stage as claimed in claim 1, characterized in that the current amplification of the amplifier stage is at least partially determined by the widths of the input gate, of the at least one gate, and of the output gate, and by the overlap of the injecting emitter of the output gate with the input of the output gate.
Claim 9
Dependent Claim
39 words
An amplifier stage of claim 1 in which the stage is arranged on a p + doped silicon layer and a p conducting epitaxial layer, the epitaxial layer being divided into individual troughs in which the gates are arranged.
Claim 10
Dependent Claim
277 words
An arrangement in which integrated injection (I 2 L) circuits are supplied with differing currents, comprising: (a) a first I 2 L circuit having a transistor with an injecting emitter and connected via said injecting emitter to a first injector path; (b) a further I 2 L circuit having a transistor with an injecting emitter connected via said injecting emitter to a further injector path; (c) differing currents flowing in the first and further injector paths; (d) an amplifier stage including (i) a current hogging injection logic (CHIL) input gate having a transistor with an injecting emitter, an output, and an input; (ii) at least one gate having a transistor with an injecting emitter, an output, and an input; (iii) a CHIL output gate having a transistor with an injecting emitter, an output, and an input; (e) the CHIL input gate input being connected to an output of the first I 2 circuit and the CHIL output gate output being connected to an input of the further I 2 L circuit; (f) the CHIL input gate injecting emitter being connected to the first injector path; (g) the CHIL output gate injecting emitter being connected to the further injector path and by its input coupled to the first injector path; (h) the CHIL input gate output being connected to the input of the at least one gate; and (i) the at least one gate output being connected to the input of the CHIL output gate; whereby the current at the output of the first I 2 L circuit is amplified in steped fashion via the CHIL input gate, the at least one gate, and the CHIL output gate.
Claim 11
Dependent Claim
277 words
An arrangement in which integrated injection (I 2 L) circuits are supplied with differing currents, comprising: (a) a first I 2 L circuit having a transistor with an injecting emitter and connected via said injecting emitter to a first injector path; (b) a further I 2 L circuit having a transistor with an injecting emitter connected via said injecting emitter to a further injector path; (c) differing currents flowing in the first and further injector paths; (d) an amplifier stage including (i) a current hogging injection logic (CHIL) input gate having a transistor with an injecting emitter, an output, and an input; (ii) at least one gate having a transistor with an injecting emitter, an output, and an input; (iii) a CHIL output gate having a transistor with an injecting emitter, an output, and an input; (e) the CHIL input gate input being connected to an output of the first I 2 circuit and the CHIL output gate output being connected to an input of the further I 2 L circuit; (f) the CHIL input gate injecting emitter being connected to the first injector path; (g) the CHIL output gate injecting emitter being connected to the further injector path and by its input coupled to the first injector path; (h) the CHIL input gate output being connected to the input of the at least one gate; and (i) the at least one gate output being connected to the input of the CHIL output gate; whereby the current at the output of the first I 2 L circuit is amplified in steped fashion via the CHIL input gate, the at least one gate, and the CHIL output gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |