Automatic compensating circuit

Claim 2

A drift compensated signal level shifter comprising the combination of a difference amplifier having a pair of inputs and an output; means for applying an input signal to one of the inputs of said amplifier, said input signal having a predetermined initial set point voltage level; a controllable voltage source for applying a level shifting voltage to the other input of said amplifier to thereby produce a level shifted version of said input signal at the output of said amplifier, said level shifting voltage having a predetermined initial level; a comparator coupled to the output of said amplifier for supplying an error signal having a first logic level whenever said level shifted signal deviates in one direction from a predetermined reference voltage and a second logic level whenever said level shifted signal deviates in the other direction from said reference voltage; and control means coupled between said comparator and said voltage source, said control means being allotted a predetermined period of time for incrementally adjusting the level of said level shifting voltage whenever said error signal is at said first logic level during said period of time, whereby compensation is provided for any drift in a first direction of said input signal from said set point voltage level.

Claim 3

The signal level shifter of claim 1 wherein said controllable voltage source comprises counter means for incrementally accumulating a count, and digital to analog converter means coupled between said counter means and said other input of said difference amplifier, said converter means adjusting said level shifting voltage in discrete voltage increments as said counter means accumulates said count.

Claim 4

The signal level shifter of claim 2 wherein said digital to analog converter means comprises a fixed voltage source for setting the initial level of said level shifting voltage, binary weighted resistor network means coupled to said counter means for adjusting a drift compensating voltage in discrete voltage increments as said counter means accumulates said count, and means for summing the voltage from said fixed voltage source with the voltage from said binary weighted resistor network means to apply a drift compensated level shifting voltage to said other input of said amplifier.

Claim 5

The signal level shifter of claim 2 wherein said control means includes a source of incrementing pulses for said counter means, gate means for coupling said incrementing pulses to said counter means, and means for enabling said gate means to pass said incrementing pulses to said counter means when said error signal is at said first logic level and for disabling said gate means when said error signal is at said second logic level.

Claim 6

The signal level shifter of claim 2 further comprising decoder means responsive to said counter means accumulating a predetermined count for generating a disabling signal, said control means including means for inhibiting further incrementing of said counter means in response to said disabling signal.

Claim 7

In a communications system with a receiving terminal for responding to an input signal having a predetermined carrier frequency and including an unmodulated portion followed by an information modulated portion; said receiving terminal including a carrier detector for responding to said input signal to provide a detect signal having a first logic level in the presence of said input signal and a second logic level in the absence of said input signal, and a demodulator for providing a demodulated signal in response to said input signal; the improvement comprising a drift compensated signal level shifter in said receiving terminal for shifting the voltage level of said demodulated signal; said signal level shifter including a difference amplifier having a pair of inputs and an output, means for applying said demodulated signal to one of the inputs of said amplifier, a controllable voltage source for applying a level shifting voltage to the other input of said amplifier, whereby a level shifted version of said demodulated signal appears at the output of said amplifier, a comparator coupled to the output of said amplifier for comparing said level shifted signal against a reference voltage to provide an error signal having a first logic level whenever said level shifted signal deviates in one direction from said reference voltage and a second logic level whenever said level shifted voltage deviates in the opposite direction from said reference voltage, said reference voltage being selected to define one end of a permissible range for said level shifted signal when said input signal is at said carrier frequency, and control means coupled between said comparator and said voltage source for incrementally adjusting said level shifting voltage when said error signal is at said first logic level, while said input signal is at said carrier frequency, and in a manner tending to bring said level shifted signal within said range.

Claim 8

In a communications system with a receiving terminal for responding to an input signal having a predetermined carrier frequency and including an unmodulated portion followed by an information modulated portion; said receiving terminal including a carrier detector for responding to said input signal to provide a detect signal having a first logic level in the presence of said input signal and a second logic level in the absence of said input signal, and a demodulator for providing a demodulated signal in response to said input signal; the improvement comprising a drift compensated signal level shifter in said receiving terminal for shifting the voltage level of said demodulated signal; said signal level shifter including a difference amplifier having a pair of inputs and an output, means for applying said demodulated signal to one of the inputs of said amplifier, a controllable voltage source for applying a level shifting voltage to the other input of said amplifier, whereby a level shifted version of said demodulated signal appears at the output of said amplifier, a comparator coupled to the output of said amplifier for comparing said level shifted signal against a reference voltage to provide an error signal having a first logic level whenever said level shifted signal deviates in one direction from said reference voltage and a second logic level whenever said level shifted voltage deviates in the opposite direction from said reference voltage, said reference voltage being selected to define one end of a permissible range for said level shifted signal when said input signal is at said carrier frequency, and control means coupled between said comparator and said voltage source for incrementally adjusting said level shifting voltage when said error signal is at said first logic level, while said input signal is at said carrier frequency, and in a manner tending to bring said level shifted signal within said range.

Claim 9

The improvement of claim 6 wherein said controllable voltage source includes means for supplying a fixed voltage, a counter for accumulating a count in response to clock pulses, means for resetting said counter whenever said detect signal goes to said second logic level, whereby said counter is cleared in the absence of said input signal, a binary weighted resistive network for converting the count accumulated by said counter into a compensating voltage, and means for summing said fixed voltage and said compensating voltage to provide said level shifting voltage.

Claim 10

The improvement of claim 7 wherein said control means includes a source of clock pulses, gate means coupling between said clock pulse source and said counter, and means for enabling said gate means to pass said clock pulses to said counter when said error signal is at said first logic level and for disabling said gate means when said error signal is at said second logic level.

Claim 11

The improvement of claim 8 wherein said control means further includes decoder means responsive to said counter accumulating a predetermined count for applying a disabling signal to said gate means, thereby preventing further clock pulses from passing to said counter.