Gain control circuit

Claim 2

A gain control circuit comprising: (a) an input terminal supplied with an input signal to be controlled; (b) an output terminal for deriving an output signal; (c) first and second variable impedance means connected in series between said input and output terminals; (d) first variable current source means connected to the connection point of said first and second variable impedance means; (e) second and third variable current source means respectively connected to said input and output terminals, said first, second and third variable current source means varying during gain control such that a current value of each of said second and third current sources is substantially equal to one half of that of said first current source, and the current flow directions of said second and third current sources is opposite with respect to said first current source so as to provide a source and sink for currents through the variable impedance means; and (f) a plural set of said input and output terminals, first and second variable impedance means, and first, second and third current source means are provided, and each set of said second and third current sources are controlled by a common current regulating means; whereby the output signal is controlled by varying the currents of said first, second and third current sources in such a way that the current value of said first current source equals the total current value of said second and third current sources.

Claim 3

A gain control circuit according to claim 1, in which said first and second variable impedance means comprise a pair of first and second transistors each having base, emitter and collector electrodes and having NPN type conductivity, the base electrodes thereof being connected together to said first current source, the collector-emitter circuit of said first transistor and the emitter-collector circuit of said second transistor being connected between said input and output terminals, respectively.

Claim 4

A gain control circuit comprising: (a) an input terminal supplied with an input signal to be controlled; (b) an output terminal for deriving an output signal; (c) first and second variable impedance means connected in series between said input and output terminals; (d) first current source means connected to the connection point of said first and second variable impedance means; (e) second and third current source means respectively connected to said input and output terminals in which each current value of said second and third current sources is substantially equal to one half of that of said first current source, and the current flow directions of said second and third current sources is opposite with respect to said first current source so as to provide a source and sink for currents through the variable impedance means; and (f) said first through third current sources comprising: (i) first current mirror circuit means having a pair of current supply terminals, each substantially supplying the same current therefrom, one terminal of which is connected to the connection point of said first and second variable impedance means; (ii) second current mirror circuit means having a pair of current sink terminals, each substantially sinking the same current as that of each of said current supply terminals, one terminal of which is connected to the other current supply terminal of said first current mirror circuit means; and (iii) first and second current paths, one side of each of which is connected to each other and to the other current sink terminal of said second current mirror circuit means, and each of the other sides of which is connected to said input and output terminals, respectively; whereby the output signal is controlled by varying the currents of said first, second and third current sources in such a way that the current value of said first current source equals the total current value of said second and third current sources.

Claim 5

A gain control circuit comprising: (a) an input terminal supplied with an input signal to be controlled; (b) an output terminal for deriving an output signal; (c) first and second variable impedance means connected in series between said input and output terminals; (d) first current source means connected to the connection point of said first and second variable impedance means; (e) second and third current source means respectively connected to said input and output terminals in which each current value of said second and third current sources is substantially equal to one half of that of said first current source, and the current flow directions of said second and third current sources is opposite with respect to said first current source so as to provide a source and sink for currents through the variable impedance means; and (f) said first through third current sources comprising: (i) first current mirror circuit means having a pair of current supply terminals, each substantially supplying the same current therefrom, one terminal of which is connected to the connection point of said first and second variable impedance means; (ii) second current mirror circuit means having a pair of current sink terminals, each substantially sinking the same current as that of each of said current supply terminals, one terminal of which is connected to the other current supply terminal of said first current mirror circuit means; and (iii) first and second current paths, one side of each of which is connected to each other and to the other current sink terminal of said second current mirror circuit means, and each of the other sides of which is connected to said input and output terminals, respectively; whereby the output signal is controlled by varying the currents of said first, second and third current sources in such a way that the current value of said first current source equals the total current value of said second and third current sources.

Claim 6

A gain control circuit according to claim 3, in which said first current mirror circuit means comprises: (a) a first reference DC potential; (b) a first transistor having base, emitter and collector electrodes, the emitter electrode thereof being connected to said first reference DC potential, both the base and collector electrodes thereof being connected together to a second reference DC potential; (c) a second transistor having base, emitter and collector electrodes, the emitter and base electrodes thereof being connected between the emitter and base electrodes of said first transistor, respectively; (d) a third transistor having base, emitter and collector electrodes, the collector and base electrodes thereof being connected between the emitter and collector electrodes of said second transistor, and the emitter electrode thereof being one of said current supply terminals; and (e) a fourth transistor having base, emitter and collector electrodes, the collector and base electrodes thereof being connected between the collector and base electrodes of said third transistor, and the emitter electrode thereof being the other of said current supply terminals.

Claim 7

A gain control circuit according to claim 4, in which said second current mirror circuit means comprises: (a) a fifth transistor having base, emitter and collector electrodes, the collector electrode thereof being connected to the emitter electrode of said third transistor, the emitter electrode thereof being connected to said second reference DC potential, and the base electrode thereof being connected through a direct current circuit to the collector electrode thereof; and (b) a sixth transistor having base, emitter and collector electrodes, the base electrode thereof being connected to the base electrode of said fifth transistor, the emitter electrode thereof being connected to said second reference DC potential, the collector electrode thereof being connected the connection point of said first and second current paths.

Claim 8

A gain control circuit according to claim 5, in which said first and second current paths comprise seventh and eighth transistors each having base, emitter and collector electrode, their emitter electrodes being connected to each other and to the collector electrode of said sixth transistor, their base electrodes being connected together to a third reference DC potential, and their collector electrodes being connected to said input and output terminals, respectively.

Claim 9

A gain control circuit according to claim 5, further including a ninth transistor having base, emitter and collector electrodes, the base-emitter circuit of which forms said direct current circuit of said current mirror circuit, and the collector electrode of which is connected to a fourth reference DC potential.

Claim 10

A gain control circuit according to claim 7, further including a tenth transistor having base, emitter and collector electrodes, the base electrode thereof being connected to the collector electrodes of said fifth transistor, the emitter electrode thereof being connected to the base electrode of said fifth transistor, and the collector electrode thereof being connected to the collector electrode of said sixth transistor; whereby an error with respect to the base currents of said seventh and eighth transistors is compensated by the collector current of said tenth transistor.

Claim 11

A gain control circuit according to claim 8, further including a differential amplifier comprising: (a) eleventh through fourteenth transistors each having base, emitter and collector electrodes; (b) circuit means for connecting each of the collector-emitter circuits of said eleventh and thirteenth transistors in series between said first and second reference DC potentials through a first load; (c) circuit means for connecting each of the collector-emitter circuits of said twelfth and fourteenth transistors in series between said first and second reference DC potentials through a second load; (d) circuit means for connecting the base electrodes of said thirteenth and fourteenth transistors to a fifth reference DC potential; (e) circuit means for connecting said input and output terminals between the emitter electrodes of said eleventh and twelfth transistors, respectively; (f) signal input means for supplying an input signal to at least one of base electrodes of said eleventh and twelfth transistors; and (g) signal output means connected to at least one of said first and second loads.

Claim 12

A gain control circuit according to claim 9 further including first through fourth resistors, each of said first and second resistors being interposed between said input terminal and the emitter electrode of said eleventh transistor and between said output terminal and the emitter electrode of said twelfth transistor, and said third and fourth resistors being connected between the emitter electrodes of said thirteenth and fourteenth transistors and said second reference DC potential, respectively.

Claim 13

A gain control circuit according to claim 9, further including a pair of further transistors each of which is connected to said eleventh and twelfth transistors with a Darlington configuration, respectively.