US4138739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky bipolar two-port random-access memory
Assignee: National Semiconductor Corp
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Filing: 1977-10-31
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Granted: 1979-02-06
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Expires: 1997-10-31
Abstract
Abstract High emitter-coupled logic switching speeds and low standby power are achieved with a dual-port RAM cell in which two NPN Schottky transistors in a non-saturable bistable flip-flop configuration are flanked by a second pair of transistors whose collectors are individually coupled to the flip-flop collectors. The two output digit lines of the RAM are individually connected to the emitters of the flanking transistors, and their bases are individually coupled to the two select lines. A read signal on either select line enables a flanking transistor to sense the state of the RAM. Writing is accomplished by applying a high logic signal to both select lines and one digit line while the other digit line is dropped to a low state.
Inventors
- 👤 Barry J. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:08
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; G11C11/416; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
253 words
A two-port random-access memory (i.e., RAM) cell comprising: first and second NPN transistors, the emitters of said transistors being coupled together, the base of said first transistor being coupled to the collector of said second transistor, the base of said second transistor being coupled to the collector of said first transistor; first and second resistors respectively coupled between a positive potential current source and the collectors of said first and second transistors; a third resistor coupled between the intercoupled emitters of said first and second transistors and ground reference; fourth and fifth resistors; first and second select line conductors; first and second digit line conductors; a third NPN transistor for signalling the state of the RAM cell into said first digit line conductor, the collector of said third transistor being coupled to the collector of said first transistor, the emitter of said third transistor being coupled to said first digit line conductor, and the base of said third transistor being coupled through said fourth resistor to said first select line conductor; and a fourth NPN transistor for signalling the state of the RAM cell into said second digit line conductor, the collector of said fourth transistor being coupled to the collector of said second transistor, the emitter of said fourth transistor being coupled to said second digit line conductor, and the base of said fourth transistor being coupled through said fifth resistor to said second select line conductor; said third and fourth transistors also operable for changing the state of the RAM cell.
Claim 2
Dependent Claim
253 words
A two-port random-access memory (i.e., RAM) cell comprising: first and second NPN transistors, the emitters of said transistors being coupled together, the base of said first transistor being coupled to the collector of said second transistor, the base of said second transistor being coupled to the collector of said first transistor; first and second resistors respectively coupled between a positive potential current source and the collectors of said first and second transistors; a third resistor coupled between the intercoupled emitters of said first and second transistors and ground reference; fourth and fifth resistors; first and second select line conductors; first and second digit line conductors; a third NPN transistor for signalling the state of the RAM cell into said first digit line conductor, the collector of said third transistor being coupled to the collector of said first transistor, the emitter of said third transistor being coupled to said first digit line conductor, and the base of said third transistor being coupled through said fourth resistor to said first select line conductor; and a fourth NPN transistor for signalling the state of the RAM cell into said second digit line conductor, the collector of said fourth transistor being coupled to the collector of said second transistor, the emitter of said fourth transistor being coupled to said second digit line conductor, and the base of said fourth transistor being coupled through said fifth resistor to said second select line conductor; said third and fourth transistors also operable for changing the state of the RAM cell.
Claim 3
Dependent Claim
21 words
The two-port RAM cell claimed in claim 1 wherein said first and second transistors are operated as a non-saturating bistable multivibrator.
Claim 4
Dependent Claim
18 words
The two-port RAM cell claimed in claim 1 wherein said first and second transistors are Schottky processed transistors.
Claim 5
Dependent Claim
34 words
The two-port RAM cell claimed in claim 1 wherein said third and fourth NPN transistors signal the state of said RAM cell by conducting a current into said first and second digit line conductors.
Claim 6
Dependent Claim
241 words
A two-port random-access memory (i.e., RAM) cell comprising: first and second NPN transistors, the emitters of said transistors being coupled together, the base of said first transistor being coupled to the collector of said second transistor, the base of said second transistor being coupled to the collector of said first transistor; first and second resistors respectively coupled between a positive potential current source and the collectors of said first and second transistors; a third resistor coupled between the intercoupled emitters of said first and second transistors and ground reference; first and second select line conductors; first and second digit line conductors; a third NPN transistor for signalling the state of the RAM cell into said first digit line conductor, the collector of said third transistor being coupled to the collector of said first transistor, the emitter of said third transistor being coupled to said first digit line conductor, and the base of said third transistor being coupled to said first select line conductor; and a fourth NPN transistor for signalling the state of the RAM cell into said second digit line conductor, the collector of said fourth transistor being coupled to the collector of said second transistor, the emitter of said fourth transistor being coupled to said second digit line conductor, and the base of said fourth transistor being coupled to said second select line conductor; said third and fourth transistors also operable for changing the state of the RAM cell.
Claim 7
Dependent Claim
241 words
A two-port random-access memory (i.e., RAM) cell comprising: first and second NPN transistors, the emitters of said transistors being coupled together, the base of said first transistor being coupled to the collector of said second transistor, the base of said second transistor being coupled to the collector of said first transistor; first and second resistors respectively coupled between a positive potential current source and the collectors of said first and second transistors; a third resistor coupled between the intercoupled emitters of said first and second transistors and ground reference; first and second select line conductors; first and second digit line conductors; a third NPN transistor for signalling the state of the RAM cell into said first digit line conductor, the collector of said third transistor being coupled to the collector of said first transistor, the emitter of said third transistor being coupled to said first digit line conductor, and the base of said third transistor being coupled to said first select line conductor; and a fourth NPN transistor for signalling the state of the RAM cell into said second digit line conductor, the collector of said fourth transistor being coupled to the collector of said second transistor, the emitter of said fourth transistor being coupled to said second digit line conductor, and the base of said fourth transistor being coupled to said second select line conductor; said third and fourth transistors also operable for changing the state of the RAM cell.
Claim 8
Dependent Claim
21 words
The two-port RAM cell claimed in claim 5 wherein said first and second transistors are operated as a non-saturating bistable multivibrator.
Claim 9
Dependent Claim
18 words
The two-port RAM cell claimed in claim 5 wherein said first and second transistors are Schottky processed transistors.
Claim 10
Dependent Claim
34 words
The two-port RAM cell claimed in claim 5 wherein said third and fourth NPN transistors signal the state of said RAM cell by conducting a current into said first or second digit line conductors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-05 | 1982-08-07 | 1983-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-05 | 1986-08-07 | 1987-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-05 | 1990-08-07 | 1991-02-06 | $7700.00 | Window Closed / Lapsed |