Self-contained relocatable memory subsystem

Claim 2

A self-contained relocatable memory system for use with a digital microprocessor, said digital microprocessor providing an a-bit address bus for specifying an address corresponding to a location to be read from said memory system, an n-bit bidirectional data bus for transferring data between said microprocessor and said memory system and a plurality of control signals for controlling the transfer of n-bit data constants from said microprocessor to said memory device, said microprocessor characterized as having an n-bit instruction format, said memory system comprising: an addressable memory connected to said address bus; a plurality of base registers connected to said bidirectional data bus; a plurality of gating means, each of said gating means connected to one of said plurality of base registers, each of gating means for gating the contents of its connected base register; decoder means connected between said addressable memory and each of said plurality of gating means and responsive to data patterns from said addressable memory, for selectively activating one of said plurality of gating means; Or network means connected to each of said plurality of gating means for transmitting the output of said activated gating means; an adder connected to said addressable memory and said OR network means; and driver means connected to the output of said adder and said bidirectional data bus for transmitting the output of said adder to said microprocessor.

Claim 3

The memory system in accordance with claim 1 wherein each of said base registers, in response to the receipt of one of said plurality of control signals, will store the data on said bidirectional data bus.

Claim 4

The memory system in accordance with claim 2 wherein each of said base registers is a read/write storage device.

Claim 5

The memory system in accordance with claim 3 wherein each of said base registers is further characterized as being a static memory device with a latched output.

Claim 6

The memory system in accordance with claim 2 further including means, responsive to the receipt of at least one of said control signals, for turning off the output of said driver means.

Claim 7

The memory system in accordance with claim 5 wherein said addressable memory is a read only memory.

Claim 8

The memory system in accordance with claim 6 wherein each of said base registers is further characterized as having a latched output.

Claim 9

The memory system in accordance with claim 2 or 7 wherein said OR network means includes a number of OR circuits equal to the number of bit positions contained in each of said base registers, each of said OR circuits including a number of inputs equal to the number of said base registers.

Claim 10

The memory system in accordance with claim 8 wherein the corresponding output bit position of each of said gating means is connected as an input to one of said OR circuits.

Claim 11

The memory system in accordance with claim 9 wherein each of said base registers is further characterized as a static memory.

Claim 12

The memory system in accordance with claim 5 wherein: said addressable memory is further characterized as having a storage word size of n + d bits length, where d is at least equal to 2; said addressable memory is responsive to an a bit address; and each of said base registers includes means for storing n bits of data.

Claim 13

The memory system in accordance with claim 11 wherein said decoder means is further characterized as being connected to d output bits of said addressable memory.

Claim 14

The memory system in accordance with claim 12 further characterized in that said decoder means, in response to the receipt of specified d bit data patterns from said addressable memory, will activate one of said plurality of gating means.

Claim 15

The memory system in accordance with claim 13 further characterized in that the input to said adder from said addressable memory includes n bits of the output of said addressable memory.

Claim 16

The memory system in accordance with claim 14 further characterized in that the data paths between each of said gating means and said OR network is n bits wide.

Claim 17

The memory system in accordance with claim 14 wherein said adder is further characterized as an n-bit adder.

Claim 18

A self-contained relocatable memory system comprising: an addressable memory; a plurality of base registers; a plurality of gating means, each of said gating means connected to one of said plurality of base registers, each of said gating means for gating the contents of its connected base register; decoder means connected between said addressable memory and each of said plurality of gating means and responsive to data patterns from said addressable memory, for selectively activating one of said plurality of gating means; Or network means connected to said plurality of gating means for transmitting the output of said activated gating means; and an adder connected to said addressable memory and said OR network means.

Claim 19

A self-contained relocatable memory system comprising: an addressable memory; a plurality of base registers; a plurality of gating means, each of said gating means connected to one of said plurality of base registers, each of said gating means for gating the contents of its connected base register; decoder means connected between said addressable memory and each of said plurality of gating means and responsive to data patterns from said addressable memory, for selectively activating one of said plurality of gating means; Or network means connected to said plurality of gating means for transmitting the output of said activated gating means; and an adder connected to said addressable memory and said OR network means.

Claim 20

The memory system in accordance with claim 17 further comprising driver means connected to the output of said adder for transmitting the output of said adder.

Claim 21

The memory system in accordance with claim 18 wherein each of said base registers includes a read/write storage device.

Claim 22

The memory system in accordance with claim 19 further including means, responsive to the writing of data in one of said plurality of base registers, for turning off the output of said driver means.

Claim 23

The memory system in accordance with claim 17 wherein said addressable memory is a read only memory.

Claim 24

The memory system in accordance with claim 21 wherein each of said base registers is further characterized as having a latched output.

Claim 25

The memory system in accordance with claim 22 wherein each of said base registers is further characterized as a static memory device.

Claim 26

The memory system in accordance with claim 16 or 20 or 21 wherein said OR network means includes a number of OR circuits equal to the number of bit positions contained in each of said base registers, each of said OR circuits including a number of inputs equal to the number of said base registers.

Claim 27

The memory system in accordance with claim 24 wherein the corresponding output bit position of each of said gating means is connected as an input to one of said OR circuits.

Claim 28

The memory system in accordance with claim 25 wherein said adder is further characterized as an n-bit adder.

Claim 29

A self-contained relocatable memory system for use with a digital microprocessor, said digital microprocessor providing an a-bit address bus for specifying an address corresponding to a location to be read from said memory system, an n-bit bidirectional data bus for transferring data between said microprocessor and said memory system and a plurality of control signals for controlling the transfer of n-bit data constants from said microprocessor to said memory device, said microprocessor characterized by having an n-bit instruction format, said memory system comprising: an addressable read only memory connected to said address bus, said addressable memory responsive to an a-bit address, said addressable memory characterized as having a storage word size of n + d bits length, where d is at least equal to 2; a plurality of base registers connected to said bidirectional data bus, wherein each of said base registers is a read/write storage device with a latched output, and further wherein each of said base registers in response to the receipt of one of said plurality of control signals will store the n-bits of data on said bidirectional data bus; a plurality of gating means, each of said gating means connected to one of said plurality of base registers, each of said gating means for gating the contents of its connected base register; decoder means connected between d output bits of said addressable memory and each of said pluralty of gating means and responsive to data patterns from said addressable memory, for selectively activating one of said plurality of gating means; Or network means connected to each of said plurality of gating means for transmitting the output of said activated gating means, said OR network means including a number of OR circuits equal to the number of bit positions contained in each of said base registers, each of said OR circuits including a number of inputs equal to the number of said base registers, wherein the corresponding output bit position of each of said gating means is connected as an input to one of said OR circuits; an n-bit adder, said adder receiving one set of inputs from the n output bits of said addressable memory and a second set of inputs from said OR network means; driver means connected to the output of said adder and said bidirectional data bus for transmitting the output of said adder to said microprocessor; and means responsive to the receipt of at least one of said control signals for turning off the output of said driver means.

Claim 30

A self-contained relocatable memory system for use with a digital microprocessor, said digital microprocessor providing an a-bit address bus for specifying an address corresponding to a location to be read from said memory system, an n-bit bidirectional data bus for transferring data between said microprocessor and said memory system and a plurality of control signals for controlling the transfer of n-bit data constants from said microprocessor to said memory device, said microprocessor characterized by having an n-bit instruction format, said memory system comprising: an addressable read only memory connected to said address bus, said addressable memory responsive to an a-bit address, said addressable memory characterized as having a storage word size of n + d bits length, where d is at least equal to 2; a plurality of base registers connected to said bidirectional data bus, wherein each of said base registers is a read/write storage device with a latched output, and further wherein each of said base registers in response to the receipt of one of said plurality of control signals will store the n-bits of data on said bidirectional data bus; a plurality of gating means, each of said gating means connected to one of said plurality of base registers, each of said gating means for gating the contents of its connected base register; decoder means connected between d output bits of said addressable memory and each of said pluralty of gating means and responsive to data patterns from said addressable memory, for selectively activating one of said plurality of gating means; Or network means connected to each of said plurality of gating means for transmitting the output of said activated gating means, said OR network means including a number of OR circuits equal to the number of bit positions contained in each of said base registers, each of said OR circuits including a number of inputs equal to the number of said base registers, wherein the corresponding output bit position of each of said gating means is connected as an input to one of said OR circuits; an n-bit adder, said adder receiving one set of inputs from the n output bits of said addressable memory and a second set of inputs from said OR network means; driver means connected to the output of said adder and said bidirectional data bus for transmitting the output of said adder to said microprocessor; and means responsive to the receipt of at least one of said control signals for turning off the output of said driver means.