Patent US4136334A successfully refreshed from Google Patents.
US4136334A
Expired / Lapsed
US
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Timed alarming using logical inverters
Assignee: DIGEQUIP SECURITY IND Inc
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Filing: 1977-06-21
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Granted: 1979-01-23
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Expires: 1997-06-21
Abstract
Abstract A triggered before disarmed alarm system especially useful in connection with an automobile alarm uses CMOS circuitry and appropriate supply filtering having one hex-inverter integrated circuit as the only active component beside the output transistor. Diodes couple a negative immediate trigger, positive and negative delayed triggers and a disarm potential to various ones of the six inverters to render the output transistor conductive and signify an alarm condition only when an alarm condition is signified by a sequence of inputs consistent with unauthorized entry.
Inventors
- 👤 Monte G. Seifers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:01
CPC Classifications
G; G08; G08B; G08B25/00; G08B25/008; B; B60; B60R; B60R25/00; B60R25/10; B60R25/1003
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
Alarm circuitry comprising, an immediate trigger input for receiving a signal for causing an immediate alarm condition in the absence of a disarm signal, at least one delayed trigger input for receiving an alarm triggering signal for providing an alarm condition only if a disarm signal remains absent for a predetermined time interval, a disarm input for receiving said disarm signal, an output logical inverter means for providing an alarm signal only in response to the occurrence of an immediate trigger signal on said immediate trigger input concurrently with the absence of a disarm signal on said disarm input and/or the occurrence of a delayed trigger signal on said delayed trigger input and the absence of a disarm signal on said disarm input outside a predetermined delay interval, and means for intercoupling said inputs and said output inverter, the latter means for intercoupling consisting only of diodes, resistors, capacitors and inverters, whereby the quiescent current drawn by said circuitry in the absence of an alarm condition is negligible.
Claim 2
Dependent Claim
168 words
Alarm circuitry comprising, an immediate trigger input for receiving a signal for causing an immediate alarm condition in the absence of a disarm signal, at least one delayed trigger input for receiving an alarm triggering signal for providing an alarm condition only if a disarm signal remains absent for a predetermined time interval, a disarm input for receiving said disarm signal, an output logical inverter means for providing an alarm signal only in response to the occurrence of an immediate trigger signal on said immediate trigger input concurrently with the absence of a disarm signal on said disarm input and/or the occurrence of a delayed trigger signal on said delayed trigger input and the absence of a disarm signal on said disarm input outside a predetermined delay interval, and means for intercoupling said inputs and said output inverter, the latter means for intercoupling consisting only of diodes, resistors, capacitors and inverters, whereby the quiescent current drawn by said circuitry in the absence of an alarm condition is negligible.
Claim 3
Dependent Claim
17 words
Alarm circuitry in accordance with claim 1 wherein said inverters consist of a single hex-inverter integrated circuit.
Claim 4
Dependent Claim
26 words
Alarm circuitry in accordance with claim 2 and further comprising a normally nonconductive output transistor for providing an output current when enabled by said output inverter.
Claim 5
Dependent Claim
50 words
Alarm circuitry in accordance with claim 2 wherein said means for intercoupling includes means comprising an A inverter for coupling said immediate trigger input to said output inverter, and means including cascaded D and E inverters for coupling said delayed trigger input and said disarm input to said output inverter.
Claim 6
Dependent Claim
32 words
Alarm circuitry in accordance with claim 4 wherein said means for intercoupling further comprises means including a B inverter for coupling said delayed trigger input to said cascaded D and E inverters.
Claim 7
Dependent Claim
34 words
Alarm circuitry in accordance with claim 5 wherein said means for intercoupling further comprises a C inverter comprising means for coupling said disarm input to the input of said cascaded D and E inverters.
Claim 8
Dependent Claim
75 words
Alarm circuitry in accordance with claim 6 wherein said means for intercoupling comprises a capacitor connected to the input of said output inverter and through resistive means to the output of said cascaded D and E inverters for furnishing a delay of the inversion by said F inverter in the absence of a signal on said negative immediate trigger and the absence of a disarm signal on said disarm input outside a predetermined delay interval.
Claim 9
Dependent Claim
45 words
Alarm circuitry in accordance with claim 7 wherein said means for intercoupling includes a resistor capacitance network direct coupled to the input of said C inverter and said disarm input for furnishing a predetermined delay when a disarm signal is removed from said disarm input.
References Cited (Backward Citations)
US3858175A
Cited
US3930226A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-22 | 1982-07-24 | 1983-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-22 | 1986-07-24 | 1987-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-22 | 1990-07-24 | 1991-01-23 | $7700.00 | Window Closed / Lapsed |