Signed double precision multiplication logic

Claim 1

Apparatus for signed multiplication of two numbers to obtain a four quadrant double precision product in two's complement notation, each quantity being in serial form with the least significant bit first and accommodating a multiplier in two's complement, or unsigned notation and a multiplicand in two's complement or unsigned notation and in one of a plurality of word lengths, said apparatus comprising: (a) a multiplier register to which the multiplier bit stream of "n" bit words is supplied, each output tap of which selects and stores a successively later multiplier bit from each word for formation of a partial product, (b) a multiplicand shift register to which the multiplicand bit stream of "m" bit words is supplied having a plurality of output taps at one bit intervals, (c) a timing shift register in which a timing waveform is applied having a plurality of output taps at one bit intervals, said timing waveform having a first portion whose duration is set equal to "m" bit times for accommodating an "m" bit multiplicand word and having a second alternate portion set equal to the "n" bit times of a multiplier word, (d) a plurality of partial product selectors for forming separate partial products, (i) the "i th " selector having (1) a first input connected to an i th output tap at the multiplier register for response to the "i th " multiplier bit, (2) a second input connected to an output tap of said multiplicand register for entry of the i th multiplicand, delayed in correspondence with the significance of the multiplier bit entered, (3) a third input connected to an output tap on said timing register for application of a delayed timing waveform (t i ) having said first portion delayed to coincide with said i th multiplicand, and (4) a fourth input to which said timing waveform is applied at a predetermined delay (t r ) for halting sign extension and defining the bit times of the partial product word, (ii) said i th selector producing a partial product which consists of the shifted i th multiplicand gated by the i th multiplier bit preceded by zero or more zeros and succeeded by one or more extensions of the last or sign bit, and (e) a summation network in which all said partial products are combined, including means for negating said last partial product if a multiplier sign bit denoting a negative multiplier is entered in said last partial product selector, said summation network consolidating the bit streams representing said sign extended partial products into a sigle bit stream to form a double precision product.