Time-shared sample and hold circuit

Claim 2

In a television receiver having a plurality of amplitude controlled stages, a time-shared sample and hold circuit comprising: a plurality of level detecting means connected to respective ones of said controlled stages for receiving respective signals and for providing outputs representative of the amplitude thereof; monitoring means connected to said level detecting means for providing an output representative of the operation thereof; resetting means connected to said monitoring means and to said level detecting means for resetting said level detecting means in response to a prescribed operating condition thereof; and commutating means connected to said monitoring means and to said resetting means for enabling said monitoring means to alternatively monitor the operation of selected ones of said level detecting means and for providing a signal to said resetting means so that said selected ones of said level detecting means are reset in response to said prescribed operating conditions.

Claim 3

A time-shared sample and hold circuit as defined in claim 1 wherein said monitoring means includes a sensing means connected to said level detecting means for providing an output representative of the operation thereof.

Claim 4

A time-shared sample and hold circuit as defined in claim 2 wherein said monitoring means further includes a sampling means connected to said sensing means and to said commutating means for providing an output representative of the operation of selected ones of said level detecting means, as determined by the output condition of said commutating means.

Claim 5

A time-shared sample and hold circuit as defined in claim 3 wherein said sampling means comprises: a logic circuit having inputs connected to said sensing means and said commutating means; a discharge circuit having an input connected to an output of said logic circuit; and a delay circuit connected to the output of said discharge circuit and to said commutating means.

Claim 6

A time-shared sample and hold circuit as defined in claim 4 wherein said logic circuit provides an output representative of selected ones of said level detection means as determined by the output condition of said commutating means.

Claim 7

A time-shared sample and hold circuit as defined in claim 5 wherein said discharge circuit includes an electron device rendered conductive in response to the output of said logic circuit.

Claim 8

A time-shared sample and hold circuit as defined in claim 4 wherein said delay circuit determines the length of time required for said reset means to respond to said prescribed operating condition of said level detecting means.

Claim 9

The time-shared sample and hold circuit as defined in claim 1 wherein said commutating means further includes a pulse shaper connected to a source of input trigger signals for providing a fixed amplitude output pulse; a comparator means connected to said pulse shaper means and said monitor means for providing an output representative of the relative outputs thereof; and monitor reset means connected to said monitoring means and comparator means for resetting said monitoring means in response to the output of said comparator means.

Claim 10

A time-shared sample and hold circuit as defined in claim 8 wherein said commutating means further includes a binary electronic device for providing a plurality of output conditions in response to an input trigger signal.

Claim 11

A time-shared sample and hold circuit as defined in claim 9 wherein said commutating means further includes a pulse shaper connected to a source of signals occurring during the vertical retrace period.

Claim 12

A time-shared sample and hold circuit as defined in claim 1 wherein said resetting means includes: comparator means having a first input connected to the output of said monitoring means, a second input connected to a source of potential, and an output responsive to the relative amplitudes of signals present at said inputs; a logic circuit having inputs connected to the output of said comparator means and said commutating means; and a plurality of discharge means having inputs connected to the output of said logic circuit and outputs connected to respective areas of said level detecting means.

Claim 13

A time-shared sample and hold circuit as defined in claim 11 wherein each of said discharge means includes an electron device rendered conductive in response to the output of said logic circuit.

Claim 14

In a television receiver having a plurality of amplitude control means, a time-shared sample and hold circuit comprising: a plurality of level detecting means, connected to said control means, each coupled to receive a respective signal, for providing an output representative of the amplitude thereof; a plurality of sensing means connected to respective ones of said level detecting means for providing outputs representative of the operation thereof; sampling means connected to said sensing means for providing an output representative of selected ones of said sensing means; a delay circuit connected to the output of said sampling means; commutating means connected to said sampling means for determining which of said sensing means are sampled to affect the output of said delay circuit; and resetting means connected to said commutating means, said level detecting means and said delay circuit for resetting selected ones of said level detecting means in response to a prescribed output condition of said delay circuit.

Claim 15

In a television receiver having a plurality of amplitude control means, a time-shared sample and hold circuit comprising: a plurality of level detecting means, connected to said control means, each coupled to receive a respective signal, for providing an output representative of the amplitude thereof; a plurality of sensing means connected to respective ones of said level detecting means for providing outputs representative of the operation thereof; sampling means connected to said sensing means for providing an output representative of selected ones of said sensing means; a delay circuit connected to the output of said sampling means; commutating means connected to said sampling means for determining which of said sensing means are sampled to affect the output of said delay circuit; and resetting means connected to said commutating means, said level detecting means and said delay circuit for resetting selected ones of said level detecting means in response to a prescribed output condition of said delay circuit.

Claim 16

The time-shared sample and hold circuit as defined in claim 13 wherein said sampling means includes: a logic circuit having inputs connected to said sensing means and said commutating means; and a discharge circuit having a plurality of electron devices rendered conductive in response to the output of said logic circuit.

Claim 17

The time-shared sample and hold circuit as defined in claim 14 wherein said delay circuit includes a resistive branch and a reactive branch connected between first and second sources of potential.

Claim 18

The time-shared sample and hold circuit as defined in claim 15 wherein said commutating means provides a number of output conditions varying in response to a trigger signal, said trigger signal being disabled in reaction to a prescribed output condition of said delay circuit.