Circuit for testing high frequency current amplifying capability of bipolar transistors

Claim 2

A transistor test circuit for testing the high frequency current amplifying capability of bipolar transistors having widely varying current gains and cut-off frequencies, said circuit comprising: emitter, collector and base connecting terminals to which the emitter, collector and base terminals of the transistors under test are respectively to be connected, means providing at a test signal input terminal a sinusoidal test frequency signal which has a frequency much greater than the assumed normal cut-off frequency of the transistors to be tested, a source of DC energizing voltage, test circuit means coupled between said source of DC energizing voltage and said emitter and collector connecting terminals and between said test signal input terminal and said emitter and base connecting terminals for producing an amplifier circuit which linearly amplifies the test frequency signal when the base circuit of the transistor under test is properly biased, said test circuit means including an automatic bias level control circuit connected between said emitter and base connecting terminals and responsive to the DC collector current of the transistor under test to automatically adjust the base drive current of the transistor under test to provide a substantially fixed predetermined DC collector current effecting linear amplification of said test frequency signal, and means for providing an indication of the product of the test frequency signal and the amplitude of the AC component of the collector current of the transistor under test.

Claim 3

The transistor test circuit of claim 1 wherein said test frequency signal frequency is much less than the frequency at which the gain of the transistor under test reduces to one, wherein the gain of the transistor under test will normally be at least about two.

Claim 4

The transistor test circuit of claim 2 wherein said test frequency signal frequency is selected so that the current gain of the transistors to be tested will normally be at least about five.

Claim 5

The transistor test circuit of claim 1 wherein there is provided means for effectively providing an AC short circuit across said emitter and collector connecting terminals.

Claim 6

The transistor test circuit of claim 1 wherein said amplifier circuit which linearly amplifies includes first impedance means in a circuit between said collector connecting terminal and said source of DC energizing voltage, and there is provided means for providing the equivalent of an AC short circuit across said emitter and collector connecting terminals comprising a circuit including a second transistor having its emitter and collector respectively coupled through emitter and collector circuit impedances to a source of DC energizing voltage and its base connected to a voltage reference point providing a fixed base-emitter current, means for coupling said collector connecting terminal for the transistor under test to the emitter connected side of said emitter circuit impedance, said first impedance means of the collector circuit of the transistor under test being a small fraction of the input impedance at the point where said coupling means couples said collector connecting terminal to the emitter circuit of the second transistor so that most of the AC component of collector current bypasses said first impedance means, and means for coupling the AC component of the voltage drop across the collector circuit impedance of said second transistor to said indication providing means.

Claim 7

A transistor test circuit for testing the high frequency current amplifying capability of bipolar transistors having widely varying current gains and cut-off frequencies, said circuit comprising: emitter, collector and base connecting terminals to which the emitter, collector and base terminals of the transistors under test are respectively to be connected, means providing at a test signal input terminal a selection of at least two sinusoidal test frequency signals, each of which is much greater than the assumed normal cut-off frequencies of the transistors to be tested, a source of DC energizing voltage, test circuit means coupled between said source of DC energizing voltage and said emitter and collector connecting terminals and between said test signal input terminal and said emitter and base connecting terminals for producing an amplifier circuit which linearly amplifies the test frequency signal when the base circuit of the transistor under test is properly biased to obtain linear amplifier action, said test circuit means including an automatic bias level control circuit connected between said emitter and base connecting terminals responsive to the DC collector current to automatically adjust the base drive current of the transistor under test to provide a substantially fixed predetermined DC collector current effecting said linear amplification of the test frequency signal, and means for providing an indication of the product of said selected test frequency signal and the amplitude of the AC component of the collector current of the transistor under test.

Claim 8

A transistor test circuit for testing the high frequency current amplifying capability of bipolar transistors having widely varying current gains and cut-off frequencies, said circuit comprising: emitter, collector and base connecting terminals to which the emitter, collector and base terminals of the transistors under test are respectively to be connected, means providing at a test signal input terminal a selection of at least two sinusoidal test frequency signals, each of which is much greater than the assumed normal cut-off frequencies of the transistors to be tested, a source of DC energizing voltage, test circuit means coupled between said source of DC energizing voltage and said emitter and collector connecting terminals and between said test signal input terminal and said emitter and base connecting terminals for producing an amplifier circuit which linearly amplifies the test frequency signal when the base circuit of the transistor under test is properly biased to obtain linear amplifier action, said test circuit means including an automatic bias level control circuit connected between said emitter and base connecting terminals responsive to the DC collector current to automatically adjust the base drive current of the transistor under test to provide a substantially fixed predetermined DC collector current effecting said linear amplification of the test frequency signal, and means for providing an indication of the product of said selected test frequency signal and the amplitude of the AC component of the collector current of the transistor under test.

Claim 9

The transistor test circuit of claim 6 wherein there is provided means for effectively providing an AC short across said emitter and collector connecting terminals.

Claim 10

The transistor test circuit of claim 6 wherein said amplifier circuit which linearly amplifies includes first impedance means in a circuit between said collector connecting terminal and said source of DC energizing voltage, and there is provided means for providing the equivalent of an AC short circuit across said emitter and collector connecting terminals comprising a circuit including a second transistor having its emitter and collector respectively coupled through emitter and collector circuit impedances to a source of DC energizing voltage and its base connected to a voltage reference point providing a fixed base-emitter current, means for coupling said collector connecting terminal for the transistor under test to the emitter connected side of said emitter circuit impedance, said first impedance means of the collector circuit of the transistor under test being a small fraction of the input impedance at the point where said coupling means couples said collector connecting terminal to the emitter circuit of the second transistor so that most of the AC component of collector current bypasses said first impedance means, and means for coupling the AC component of the voltage drop across the collector circuit impedance of said second transistor to said indication providing means.

Claim 11

The transistor test circuit of claim 6 wherein said means for providing an indication includes meter movement means which moves pointer means over scale means in proportion to the current flowing therethrough, and calibration means comprising variable impedance means which varies the current in said meter movement in proportion to the selected test frequency.

Claim 12

The transistor test circuit of claim 9 wherein said meter movement means is a single meter movement having one pointer moving over a separate scale for each test frequency, each of said scales having indicia directly indicating the product of the current gain of the transistor under test and the test frequency represented by the various degrees of pointer movement.

Claim 13

The transistor test circuit of claim 6 wherein said indication providing means includes a single meter movement, and there is provided means responsive to the test frequency selected for controlling the amount of current flowing through the meter movement for a given test transistor gain depending upon the selected test frequency.

Claim 14

The transistor test circuit of claim 11 wherein said meter movement includes a pointer moving in response to the flow of current through the meter movement and a plurality of scales equal in number to the number of selectable test frequency signals over which the pointer moves, said plurality of scales being calibrated in accordance with the product of the frequency of the associated selected test frequency signal and the current gains corresponding to various deflection points of the pointer along the scales involved.

Claim 15

The transistor test circuit of claim 6 wherein said test frequency signal frequencies are only a fraction of the frequency at which the current gain of normal transistors to be tested thereby would decrease to 1.

Claim 16

The transistor test circuit of claim 6 wherein the uppermost of said test frequency signal frequencies is at least about 5 times greater than the lowermost of the same.

Claim 17

The transistor test circuit of claim 6 wherein said means providing at a test signal input terminal provides a selection of three test frequency signals, the ratio of the frequency of the intermediate to the lowermost of these test frequency signal frequencies being many times more than the ratio of the uppermost to the intermediate of these test frequency signal frequencies.

Claim 18

The transistor test circuit of claim 10 wherein said means providing at a test signal input terminal provides a selection of at least three test frequency signals of widely differing frequencies, and there are three of said scales over which said pointer moves.

Claim 19

The transistor test circuit of claim 16 wherein full scale pointer deflection on the scale used with the uppermost test frequency indicates a value in excess of about 1,000 MHz, on the scale used with the lowermost test frequency indicates a value substantially under 500 MHz, and on the scale used with the intermediate test frequency indicates a value substantially greater than full scale pointer deflection on the scale associated with the lowermost test frequency and substantially lower than the full scale pointer deflection on the scale associated with the uppermost test frequency.

Claim 20

The transistor test circuit of claim 5 wherein said means for coupling is a capacitor.