Failure-resistant pseudo-nonvolatile memory

Claim 2

A multiple bit memory circuit comprising: at least one shift register having a plurality of data bit line pairs, each pair having an input and an output, said shift register being selectably capable of operation in either synchronous or asynchronous modes and in either serial or parallel modes or any combination thereof; means for selecting said modes of operation responsive to a pattern of clock pulses generated external to said memory circuit; and clamping circuit means coupled to each of said data bit lines for storing data from said data bit lines during operation of said shift register in said serial/synchronous mode and for feeding back said data to said shift register during operation of said shift register in said parallel/asynchronous mode.

Claim 3

The memory circuit of claim 1 wherein said clamping circuit means comrpises: a first resistor having two leads and having one such lead coupled to said output data bit lines; a second resistor having two leads and having one such lead coupled to said input data bit line and having said second lead coupled to said second lead of said first resistor; and a capacitor having two leads and having one such lead coupled to said second level of said first resistor and said second lead of said second resistor and having said second capacitor lead coupled to ground.

Claim 4

A multiple bit memory circuit comprising: at least one shift register having a plurality of data bit line pairs, each pair having an input and output, said shift register being selectably capable of operation in either synchronous and asynchronous modes and in either serial or parallel modes or any combination thereof wherein said synchronous or asynchronous mode is selected by logic level input to a synchronous/asynchronous (S/A) select pin and wherein said serial or parallel mode is selected by logic level input to a serial/parallel (S/P) select pin, and having a clock input pin; a clock input port coupled to an external source of clock pulses; a clock capacitor diode coupled between said clock input port and ground; a first logic gate having inputs coupled to said clock capacitor and an output; a second logic gate having inputs coupled to said output of said first gate and having an output; a third logic gate having a first input coupled to said output of said second gate and having a second input coupled to said clock input port and having an output port coupled to said clock input pin of said shift register; wherein said (S/A) select pin is coupled to said output of said first gate and to said inputs of said second gate, and wherein said (S/P) select pin is resistor coupled to said output of said first gate and said inputs of said second gate and capacitor coupled to ground; whereby the operating modes of said shift register are selected responsive to said external source of clock pulses; and clamping circuit means coupled to said data bit lines comprising: a first resistor having two leads and having one such lead coupled to said output data bit line; a second resistor having two leads and having one such lead coupled to said input data bit line and having said second lead coupled to said second lead of said first resistor; and a capacitor having two leads and having one such lead coupled to said second lead of said first resistor and said second lead of said second resistor and having said second capacitor lead coupled to ground; whereby data from said data bit lines are stored within said clamping circuit means during operation of said shift register in said serial/synchronous mode and fed back to said data bit lines during operation of said shift register in said parallel asynchronous mode.

Claim 5

A multiple bit memory circuit comprising: at least one shift register having a plurality of data bit line pairs, each pair having an input and output, said shift register being selectably capable of operation in either synchronous and asynchronous modes and in either serial or parallel modes or any combination thereof wherein said synchronous or asynchronous mode is selected by logic level input to a synchronous/asynchronous (S/A) select pin and wherein said serial or parallel mode is selected by logic level input to a serial/parallel (S/P) select pin, and having a clock input pin; a clock input port coupled to an external source of clock pulses; a clock capacitor diode coupled between said clock input port and ground; a first logic gate having inputs coupled to said clock capacitor and an output; a second logic gate having inputs coupled to said output of said first gate and having an output; a third logic gate having a first input coupled to said output of said second gate and having a second input coupled to said clock input port and having an output port coupled to said clock input pin of said shift register; wherein said (S/A) select pin is coupled to said output of said first gate and to said inputs of said second gate, and wherein said (S/P) select pin is resistor coupled to said output of said first gate and said inputs of said second gate and capacitor coupled to ground; whereby the operating modes of said shift register are selected responsive to said external source of clock pulses; and clamping circuit means coupled to said data bit lines comprising: a first resistor having two leads and having one such lead coupled to said output data bit line; a second resistor having two leads and having one such lead coupled to said input data bit line and having said second lead coupled to said second lead of said first resistor; and a capacitor having two leads and having one such lead coupled to said second lead of said first resistor and said second lead of said second resistor and having said second capacitor lead coupled to ground; whereby data from said data bit lines are stored within said clamping circuit means during operation of said shift register in said serial/synchronous mode and fed back to said data bit lines during operation of said shift register in said parallel asynchronous mode.