Image information reading apparatus

Claim 2

An image information reading apparatus, comprising means for reading an optical image, a peak hold means, connected to the output of said means for reading an optical image, for storing the peak analog value of the output of said receiving means for a predetermined period of time, first and second means responsive to peak hold means for level detecting and converting into a succession of digital outputs the output from said peak hold means at first and second predetermined levels, respectively, that are different from each other, means coupled to said second level detecting and converting means for determining the pattern of successive digital outputs obtained by said second level detecting and converting means for providing a selection signal, and gate means coupled to said first and second level detecting and converting means and responsive to said selection signal for selectively transmitting the output of either of said first and second level detecting and converting means.

Claim 3

An image information reading apparatus in accordance with claim 1, wherein said determining means comprises pattern storage means responsive to said second level detecting and converting means for storing the successive digital outputs of said second level detecting and converting means, and means for judging the pattern of the successive digit outputs stored in said pattern store means for providing said selection signal determinable as a function of said determination.

Claim 4

An image information reading apparatus in accordance with claim 2, which further comprises delay storage means responsive to said first level detecting and converting means for storing the successive digital outputs of said first level detecting and converting means for delaying the successive digital outputs of said first level detecting and converting means for synchronization with the successive digital outputs stored in said pattern storage means.

Claim 5

An image information reading apparatus in accordance with claim 3, wherein said delay storage means and said pattern storage means each comprises first and second shift register means, respectively, for shifting said stored successive digital outputs as a function of a clock pulse, each shift register means having a plurality of bit positions.

Claim 6

An image information reading apparatus in accordance with claim 4, wherein said gate means is adapted to selectively transmit the successive digital outputs of said first or second level detecting and converting means from the corresonding bit positions of the corresponding one of said first and second shift register means.

Claim 7

A signal discriminator apparatus comprising: a means for receiving an input signal to be discriminated, a peak hold means, connected to the output of said receiving means, for storing the peak analog value of the output of said receiving means for a predetermined period of time first and second means responsive to the output of said peak hold means for level detecting and converting into a succession of digital outputs the output of said peak hold means at first and second predetermined levels, respectively, that are different from each other, means coupled to said second level detecting and converting means for determining the pattern of successive digital outputs obtained by said second level detecting and converting means for providing a selection signal, and gate means coupled to said first and second level detecting and converting means and responsive to said selection signal for selectively transmitting the output of either of said first and second level detecting and converting means.

Claim 8

A signal discriminator apparatus comprising: a means for receiving an input signal to be discriminated, a peak hold means, connected to the output of said receiving means, for storing the peak analog value of the output of said receiving means for a predetermined period of time first and second means responsive to the output of said peak hold means for level detecting and converting into a succession of digital outputs the output of said peak hold means at first and second predetermined levels, respectively, that are different from each other, means coupled to said second level detecting and converting means for determining the pattern of successive digital outputs obtained by said second level detecting and converting means for providing a selection signal, and gate means coupled to said first and second level detecting and converting means and responsive to said selection signal for selectively transmitting the output of either of said first and second level detecting and converting means.

Claim 9

An image information reading apparatus, comprising means for reading an optical image, first and second means responsive to said optical image reading means for level detecting and converting into a succession of digital outputs the output from said optical image reading means at first and second predetermined levels, respectively, that are different from each other, means coupled to said second level detecting and converting means for determining the pattern of successive digital outputs obtained by said second level detecting and converting means for providing a selection signal, and gate means coupled to said first and second level detecting and converting means and responsive to said selection signal for selectively transmitting the output of either of said first and second level detecting and converting means; wherein said determining means comprises: pattern storage means responsive to said second level detecting and converting means for storing the successive digital outputs of said second level detecting and converting means, and means for judging the pattern of the successive digit outputs stored in said pattern store means for providing said selection signal determinable as a function of said determination; and which further comprises delay storage means responsive to said first level detecting and converting means for storing the successive digital outputs of said first level detecting and converting means for delaying the successive digital outputs of said first level detecting and converting means for synchronization with the successive digital outputs stored in said pattern storage means; and wherein said delay storage means and said pattern storage means each comprises first and second shift register means, respectively, for shifting said stored successive digital outputs as a function of a clock pulse, each shift register means having a plurality of bit positions; and wherein said gate means is adapted to selectively transmit the successive digital outputs of said first or second level detecting and converting means from the corresponding bit positions of the corresponding one of said first and second shift register means; said second shift register means comprising a greater number of bit positions than said first shift register, wherein said second shift register means additionally stores successive digital outputs occurring earlier in time than those stored in said first shift register.

Claim 10

An image information reading apparatus, comprising means for reading an optical image, first and second means responsive to said optical image reading means for level detecting and converting into a succession of digital outputs the output from said optical image reading means at first and second predetermined levels, respectively, that are different from each other, means coupled to said second level detecting and converting means for determining the pattern of successive digital outputs obtained by said second level detecting and converting means for providing a selection signal, and gate means coupled to said first and second level detecting and converting means and responsive to said selection signal for selectively transmitting the output of either of said first and second level detecting and converting means; wherein said determining means comprises: pattern storage means responsive to said second level detecting and converting means for storing the successive digital outputs of said second level detecting and converting means, and means for judging the pattern of the successive digit outputs stored in said pattern store means for providing said selection signal determinable as a function of said determination; and which further comprises delay storage means responsive to said first level detecting and converting means for storing the successive digital outputs of said first level detecting and converting means for delaying the successive digital outputs of said first level detecting and converting means for synchronization with the successive digital outputs stored in said pattern storage means; and wherein said delay storage means and said pattern storage means each comprises first and second shift register means, respectively, for shifting said stored successive digital outputs as a function of a clock pulse, each shift register means having a plurality of bit positions; and wherein said gate means is adapted to selectively transmit the successive digital outputs of said first or second level detecting and converting means from the corresponding bit positions of the corresponding one of said first and second shift register means; said second shift register means comprising a greater number of bit positions than said first shift register, wherein said second shift register means additionally stores successive digital outputs occurring earlier in time than those stored in said first shift register.

Claim 11

An image information reading apparatus in accordance with claim 7, wherein said judging means comprises a read only memory preloaded with a plurality of patterns of said successive digital outputs for providing a selection signal for each of said patterns.

Claim 12

A signal discriminator apparatus comprising: an amplifier for amplifying a signal to be discriminated, a peak hold circuit connected to said amplifier output for storing the peak value of said amplifier output, first and second comparator circuits, each having first and second inputs and each having its first input connected to the output of said amplifier, first and second voltage divider means, connected to the output of said peak hold circuit, with their respective outputs connected to the second inputs of the first and second comparator circuits, wherein said first and second voltage dividers have different voltage division ratios, first and second shift registers, connected to the respective outputs of said first and second comparators, a timing signal generator means connected to said first and second shift registers for shifting said registers, a read only memory connected to the outputs of said first shift register for providing a predetermined logic output in response to said outputs of said first shift register, a gating circuit, connected to the outputs of both of said shift registers and the read only memory such that one preselected output from either said first or second shift register is outputted by said gating circuit in response to the logic level of said read only memory output.

Claim 13

A signal discriminator apparatus comprising: an amplifier for amplifying a signal to be discriminated, a peak hold circuit connected to said amplifier output for storing the peak value of said amplifier output, first and second comparator circuits, each having first and second inputs and each having its first input connected to the output of said amplifier, first and second voltage divider means, connected to the output of said peak hold circuit, with their respective outputs connected to the second inputs of the first and second comparator circuits, wherein said first and second voltage dividers have different voltage division ratios, first and second shift registers, connected to the respective outputs of said first and second comparators, a timing signal generator means connected to said first and second shift registers for shifting said registers, a read only memory connected to the outputs of said first shift register for providing a predetermined logic output in response to said outputs of said first shift register, a gating circuit, connected to the outputs of both of said shift registers and the read only memory such that one preselected output from either said first or second shift register is outputted by said gating circuit in response to the logic level of said read only memory output.