Patent US4132951A successfully refreshed from Google Patents.
US4132951A
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Digital processor controlled radio system
Assignee: Texas Instruments Inc
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Filing: 1977-04-27
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Granted: 1979-01-02
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Expires: 1997-04-27
Abstract
Abstract A radio system includes a charge transfer device transversal filter for receiving electronic input signals comprised of at least one frequency band. The charge transfer device simultaneously receives a clocking signal, and filters and frequency shifts its input signals in response to the frequency of the clocking signal. Clocking means are provided for generating the clocking signal at frequencies as indicated in digital micro commands. A digital processor has outputs coupled to the clocking means for sending the micro commands to the clocking means.
Inventors
- 👤 Michael J. Cochran
- 👤 Edward R. Caudel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:50
CPC Classifications
H; H04; H04W; H04W84/00; H03; H03D; H03D1/00; H03D1/22; H03D1/24; H03D7/00; H03H; H03H15/00; H03H15/02; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/091; H03L7/16; H03L7/18; H03L7/183; H04B; H04B1/00; H04B1/38; H04B1/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
228 words
A digital processor controlled signal processor comprising: (a) a charge transfer device transversal filter means having a selectively controllable passbandwidth centered about a finely tuneable center frequency, said filter means being coupled to simultaneously receive: (1) filter input signals comprised of a plurality of frequency bands which lie within a selected one of a plurality of non-overlapping frequency channels, and (2) a filter clocking signal of a selectable frequency f s1 , said filter means being responsive to said filter clocking signal for controlling the passbandwidth and center frequency of said filter means in response to the frequency of said clocking signal; (b) a first phase lock loop clocking means having (1) an input for receiving a reference frequency f r and (2) a feedback loop comprised of a first programmable counter means responsive to digital coded programming signals for generating in response thereto a variable count N 1 ; (c) a second programmable counter means of variable count N 2 responsive to said digital coded programming signals coupled to said clocking means for generating said filter clocking signals at said selectable frequency f s1 where f s1 = f r (N 1 /N 2 ); and (d) digital processor means responsive to logical control signals for computing the passbandwidth and center frequency of said filter means and for generating said digital coded programming signals in accordance therewith.
Claim 2
Dependent Claim
228 words
A digital processor controlled signal processor comprising: (a) a charge transfer device transversal filter means having a selectively controllable passbandwidth centered about a finely tuneable center frequency, said filter means being coupled to simultaneously receive: (1) filter input signals comprised of a plurality of frequency bands which lie within a selected one of a plurality of non-overlapping frequency channels, and (2) a filter clocking signal of a selectable frequency f s1 , said filter means being responsive to said filter clocking signal for controlling the passbandwidth and center frequency of said filter means in response to the frequency of said clocking signal; (b) a first phase lock loop clocking means having (1) an input for receiving a reference frequency f r and (2) a feedback loop comprised of a first programmable counter means responsive to digital coded programming signals for generating in response thereto a variable count N 1 ; (c) a second programmable counter means of variable count N 2 responsive to said digital coded programming signals coupled to said clocking means for generating said filter clocking signals at said selectable frequency f s1 where f s1 = f r (N 1 /N 2 ); and (d) digital processor means responsive to logical control signals for computing the passbandwidth and center frequency of said filter means and for generating said digital coded programming signals in accordance therewith.
Claim 3
Dependent Claim
215 words
The signal processor according to claim 1 including: (a) signal mixer means having inputs coupled to simultaneously receive: (1) input signals comprised of a plurality of non-overlapping frequency channels with each channel containing a plurality of frequency bands, and (2) a mixer clocking signal of a selectable frequency f s2 for frequency shifting the center frequency of a selected one of said frequency channels to a predetermined frequency; (b) a second phase lock loop clocking means having (1) an input for receiving a reference frequency f r2 and a feedback loop comprised of a third programmable counter means responsive to second digital coded programming signals for generating a variable count N 3 ; (c) a fourth counter means of variable count N 4 responsive to said second digital coded programming signals coupled to said second clocking means for generating said mixer clocking signals at said selectable frequency f s2 where f s2 = f r2 (N 3 /N 4 ), said digital processor means being responsive to said logical control signals for computing the difference between the center frequency of said selected one of said frequency channels and said predetermined frequency for generating said second digital coded programming signals in accordance with said difference; and (d) means coupling said mixer means to said filter means.
Claim 4
Dependent Claim
102 words
The signal processor according to claim 2 further including sampling demodulator means having a signal input coupled to said filter means for receiving therefrom filtered signals of a selected bandwidth and selected center frequency, and a sampling input coupled to receive a sampling clock signal f s3 ; and a fifth programmable counter means of variable count N 5 coupling said first phase lock loop clocking means to said sampling input, said fifth counter means being responsive to third digital coded programming signals for generating said sampling clock signal f s3 wherein f s3 = f r (N 1 /N 5 ).
Claim 5
Dependent Claim
75 words
The signal processor according to claim 3 further including modulator means having inputs coupled to simultaneously receive said sampling clock signals f s3 and information signals for modulating said information signals by f r (N 1 /N 5 ) and including second signal mixer means having inputs coupled to simultaneously receive said mixer clocking signals f s2 and said modulated information signals for mixing said information signals by f r (N 3 /N 4 ).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-01 | 1982-07-03 | 1983-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-01 | 1986-07-03 | 1987-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-01 | 1990-07-03 | 1991-01-02 | $7700.00 | Window Closed / Lapsed |