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US4130802A
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Unidirectional phase shift keyed communication system
Assignee: RCA Corp
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Filing: 1976-01-15
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Granted: 1978-12-19
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Expires: 1996-01-15
Abstract
Abstract A unidirectional phase shift keyed (UPSK) communication system wherein the data sequence to either an in-phase channel or a quadrature channel is delayed by a one-half bit period with respect to the data sequence to the other channel whereby bi-phase modulation is effected in phase shift steps in a predetermined phasor direction.
Inventors
- 👤 Edward J. Nossen
- 👤 Vytas F. Volertas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:28
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2071; H04L27/0014; H04L2027/0018
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
161 words
In a binary data communication system of the type including a transmitter and receiver, said transmitter comprising a data source means for supplying binary data signals having a predetermined bit period, first means for generating first and second carrier signals, said second carrier signal being substantially in quadrature with said first carrier signal, second means responsive to said first and second carrier signals and said data signals for phase-modulating said first and second carrier signals by said binary data signals, and third means for generating an output signal representative of the sum of said phase-modulated signals, the improvement wherein: said transmitter further includes fourth means for delaying by substantially half the bit period of said data signals the modulation of one of said first and second carrier signals with respect to the other, whereby phase shifting is effected in steps in a predetermined phasor direction to reduce sidebands in the frequency spectrum of the output signal generated by said third means.
Claim 2
Dependent Claim
161 words
In a binary data communication system of the type including a transmitter and receiver, said transmitter comprising a data source means for supplying binary data signals having a predetermined bit period, first means for generating first and second carrier signals, said second carrier signal being substantially in quadrature with said first carrier signal, second means responsive to said first and second carrier signals and said data signals for phase-modulating said first and second carrier signals by said binary data signals, and third means for generating an output signal representative of the sum of said phase-modulated signals, the improvement wherein: said transmitter further includes fourth means for delaying by substantially half the bit period of said data signals the modulation of one of said first and second carrier signals with respect to the other, whereby phase shifting is effected in steps in a predetermined phasor direction to reduce sidebands in the frequency spectrum of the output signal generated by said third means.
Claim 3
Dependent Claim
41 words
The system of claim 1 wherein said fourth means further includes fifth means for alternating at a transition rate said delay between said first and second carrier signals, said transition rate being less than the bit rate of said data signal.
Claim 4
Dependent Claim
140 words
The system of claim 2 wherein said second means comprises first and second phase modulators, responsive to said data signal and respectively to said first and second carrier signals, and wherein further said fifth means comprises: sixth means for generating first and second clock signals at said bit rate, said second clock signal being delayed by one half cycle with respect to said first clock signal, seventh and eighth means, each responsive to said data signal and respective control signals applied thereto, for temporarily storing the instantaneous values of said data signal in response to said respective control signals, said seventh and eighth means respectively applying signals indicative of said values to said first and second phase modulator; and ninth means, for switchably applying said first and second clock signals to said seventh and eighth means as said control signals.
Claim 5
Dependent Claim
50 words
The system of claim 3 wherein said fifth means further includes: tenth means, responsive to one of said clock signals, for deriving therefrom a switching signal, said switching signal being applied to said ninth means to effect periodic switching of said respective clock signals between said seventh and eighth means.
Claim 6
Dependent Claim
35 words
The system of claim 4 wherein said tenth means comprises a divider receptive of said one clock signal, for generating one pulse in response to a predetermined number of pulses in said one clock signal.
Claim 7
Dependent Claim
43 words
The system of claim 5 wherein said data consists of a plurality of words, each of said words consisting of a predetermined plurality of bits and wherein further said predetermined number is equal to the number of bits in one of said words.
Claim 8
Dependent Claim
56 words
The system of claim 2 wherein said second means comprises first and second phase modulators, responsive to said data signal and respectively to said first and second carrier signals and wherein further said fifth means comprises, sixth means, receptive of said data signal for periodically complementing the data signal applied to one of said phase modulators.
Claim 9
Dependent Claim
53 words
The system of claim 7 wherein said fifth means further includes seventh means, receptive of a signal indicative of said bit rate, for generating a complementing signal, said complementing signal being applied to said sixth means to effect said periodic complementing in accordance with the cumulative duration of a predetermined number of bits.
Claim 10
Dependent Claim
41 words
The system of claim 8 wherein said data consists of a plurality of words, each word consisting of a predetermined plurality of bits, wherein further said predetermined number is equal to said predetermined plurality of bits in one of said words.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-18 | 1982-06-19 | 1982-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-18 | 1986-06-19 | 1986-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-18 | 1990-06-19 | 1990-12-19 | $7700.00 | Window Closed / Lapsed |