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US4130764A
Expired / Lapsed
US
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Fail-safe or logic circuit
Assignee: Trane US Inc
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Filing: 1977-07-27
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Granted: 1978-12-19
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Expires: 1997-07-27
Abstract
Abstract A fail-safe "OR" logic gate circuit which includes at least a first and a second level detector each of which has a voltage breakdown device and an oscillating circuit, a resonant tank circuit connected in common with each of the oscillating circuits, an amplifying circuit coupled to each oscillating circuit, and a regulating-rectifying circuit coupled to the amplifying circuit and producing a d.c. output signal when a d.c. input signal causes either or both of the voltage breakdown devices to breakdown and to exhibit a low impedance for causing the oscillating circuits to oscillate and supply a.c. signals to the amplifying circuit for rectification by the regulating-rectifying circuit.
Inventors
- 👤 John O. G. Darrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/007
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
122 words
A vital logic circuit comprising at least a first and a second fail-safe level detector, each of said first and said second fail-safe level detecting means including a voltage breakdown device and an oscillating circuit, a frequency determining circuit connected in common with each of said oscillating circuits, an amplifying means coupled to each of said oscillating circuits, and an output means connected to said amplifying circuit and producing an output signal either when a d.c. input signal exceeds the breakdown voltage of one of said breakdown devices of said first and second fail-safe level detecting means or when d.c. input signals exceed the breakdown voltages of both of said breakdown devices of said first and said second fail-safe level detecting means.
Claim 2
Dependent Claim
122 words
A vital logic circuit comprising at least a first and a second fail-safe level detector, each of said first and said second fail-safe level detecting means including a voltage breakdown device and an oscillating circuit, a frequency determining circuit connected in common with each of said oscillating circuits, an amplifying means coupled to each of said oscillating circuits, and an output means connected to said amplifying circuit and producing an output signal either when a d.c. input signal exceeds the breakdown voltage of one of said breakdown devices of said first and second fail-safe level detecting means or when d.c. input signals exceed the breakdown voltages of both of said breakdown devices of said first and said second fail-safe level detecting means.
Claim 3
Dependent Claim
19 words
The vital logic circuit as defined in claim 1, wherein said frequency determining circuit is an L-C tank circuit.
Claim 4
Dependent Claim
19 words
The vital logic circuit as defined in claim 1, wherein said first oscillating circuit includes a common-emitter Colpitts oscillator.
Claim 5
Dependent Claim
19 words
The vital logic circuit as defined in claim 1, wherein said second oscillating circuit includes a common-emitter Colpitts oscillator.
Claim 6
Dependent Claim
33 words
The vital logic circuit as defined in claim 1, wherein a current-limiting resistor is connected in series with each of said voltage breakdown devices of said first and second fail-safe level detecting means.
Claim 7
Dependent Claim
77 words
The vital logic circuit as defined in claim 1, wherein said frequency determining circuit is capacitively connected to said oscillating circuits of said first and second fail-safe level detecting means such that the loss of the capacitive connection will cause the loss of the output of one of said first and second level detectors thereby guaranteeing that said first and second level detectors are unable to deliver both outputs unless said outputs have substantially the same frequency.
Claim 8
Dependent Claim
24 words
The vital logic circuit as defined in claim 1, wherein said output means includes a regulating rectifier voltage breakdown means and a capacitance means.
Claim 9
Dependent Claim
28 words
The vital logic circuit as defined in claim 1, wherein each of said oscillating circuits of said first and second fail-safe level detecting means includes a NPN transistor.
Claim 10
Dependent Claim
19 words
The vital logic circuit as defined in claim 1, wherein said frequency determining circuit is a parallel resonant network.
Claim 11
Dependent Claim
25 words
The vital logic circuit as defined in claim 1, wherein a series resistor and capacitor couples each of said oscillating circuits to said amplifying means.
Claim 12
Dependent Claim
128 words
A fail-safe "OR" gate comprising a pair of level detectors, each of which includes a voltage regulator and a regenerative feedback oscillator, each of said regulators including a current-limiting resistor and a voltage breakdown device, each of said regenerative feedback oscillators including a semiconductive amplifier which oscillates at a frequency determined by an L-C resonant circuit, each of said regenerative feedback oscillators connected to a power amplifier which supplies a.c. signals to a regulating rectifier for producing a d.c. output signal when a d.c. input causes either or both of said voltage regulators of said pair of level detectors to breakdown and conduct for causing either or both of said oscillators of said pair of level detectors to oscillate at the frequency determined by said L-C resonant circuit.
Claim 13
Dependent Claim
128 words
A fail-safe "OR" gate comprising a pair of level detectors, each of which includes a voltage regulator and a regenerative feedback oscillator, each of said regulators including a current-limiting resistor and a voltage breakdown device, each of said regenerative feedback oscillators including a semiconductive amplifier which oscillates at a frequency determined by an L-C resonant circuit, each of said regenerative feedback oscillators connected to a power amplifier which supplies a.c. signals to a regulating rectifier for producing a d.c. output signal when a d.c. input causes either or both of said voltage regulators of said pair of level detectors to breakdown and conduct for causing either or both of said oscillators of said pair of level detectors to oscillate at the frequency determined by said L-C resonant circuit.
References Cited (Backward Citations)
US3422284A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-18 | 1982-06-19 | 1982-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-18 | 1986-06-19 | 1986-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-18 | 1990-06-19 | 1990-12-19 | $7700.00 | Window Closed / Lapsed |