Differential detection systems with non-redundant error correction

Claim 1

A differential detection system with non-redundant error correction comprising first delay means for delaying by n (n is an interger) signaling intervals a received signal comprising a carrier wave modulated by m (m is an interger) level digital data; a first phase comparator for comparing the phase of the output of said first delay means and the phase of a signal received in the present signaling interval to detect a first symbol; second delay means for delaying said first mentioned received signal by 2n signaling intervals; a second phase comparator for comparing the phase of the output of said second delay means and the phase of the signal received in the present signaling interval to detect a second symbol; and a decoder responsive to the first and second symbols produced by said first and second phase comparators respectively, said decoder comprising third delay means for delaying said first symbol by n signaling intervals, a first modulo m adder for performing a modulo m addition operation of the output of said third delay means and said first symbol, a second modulo m adder for performing a modulo m addition operation of the output of said first modulo m adder and an inverted output of said second phase comparator, a third modulo m adder connected to receive the output of said second modulo m adder, fourth delay means for delaying the output of said third modulo m adder by n signaling intervals, a logic circuit for determining the coincidence between the output of said fourth delay means and the output of said second modulo m adder, a fourth modulo m adder for performing a modulo m addition operation of an inverted output of said logic circuit and the output of said third delay means, and means for applying said inverted output of said logic circuit to one input of said third modulo m adder.