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US4127810A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital voltmeter

Assignee: Ideal Industries Inc
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Filing: 1977-03-21
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Granted: 1978-11-28
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Expires: 1997-03-21
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Abstract

Abstract An analog to digital converter for use in a digital voltmeter includes a periodic source of reference signal in ramp form starting at a negative potential and increasing to a given positive potential. The ramp signal and an analog signal to be measured form the inputs for a first comparator which provides a given output level as long as the ramp signal is less than the analog signal. A source of clock signals and the output of the first comparator are connected to a first logic circuit which provides an output of clock signals during the period that the first comparator is at the given level. A second comparator is connected to the ramp signal and ground potential and provides a given output level until the ramp signal reaches ground potential. A second logic circuit is connected to the output of the second comparator and the first logic circuit and provides clock signals during the period that the ramp signal is above ground potential and less than the analog signal. The output from the second logic circuit is connected to counting and display means for visually indicating the voltage being measured.

Inventors

  • 👤 Donald A. Purland

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 12:27
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/25; G01R19/255; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/56

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 228 words
Apparatus for providing a digital display of a measured analog signal including a periodic source of reference signal in ramp form starting at a negative potential and increasing to a given positive potential, an analog signal to be measured, a first comparator circuit connected to said ramp signal and analog signal and providing a given output level as long as the ramp signal is less than the analog signal, a source of clock signals, first logic means connected to said first comparator and clock source for providing clock signals during the period that said first comparator is at said given level, a second comparator circuit connected to said ramp signal and ground potential and providing a given output level until said ramp signal reaches ground potential, second logic means connected to said second comparator and first logic means for providing clock signals during the period that said ramp signal is above ground potential and less than said analog signal, counting and display means connected to said second logic circuit, input terminals, a rectifier connected to said input terminals, switch means connected to said input terminals, rectifier and first comparator circuit, said rectifier comprising a pair of operational amplifiers, a first diode connected between the output of one amplifier and an input of the other, and a second diode connected between the output and input of said one amplifier.
Claim 2
Dependent Claim 228 words
Apparatus for providing a digital display of a measured analog signal including a periodic source of reference signal in ramp form starting at a negative potential and increasing to a given positive potential, an analog signal to be measured, a first comparator circuit connected to said ramp signal and analog signal and providing a given output level as long as the ramp signal is less than the analog signal, a source of clock signals, first logic means connected to said first comparator and clock source for providing clock signals during the period that said first comparator is at said given level, a second comparator circuit connected to said ramp signal and ground potential and providing a given output level until said ramp signal reaches ground potential, second logic means connected to said second comparator and first logic means for providing clock signals during the period that said ramp signal is above ground potential and less than said analog signal, counting and display means connected to said second logic circuit, input terminals, a rectifier connected to said input terminals, switch means connected to said input terminals, rectifier and first comparator circuit, said rectifier comprising a pair of operational amplifiers, a first diode connected between the output of one amplifier and an input of the other, and a second diode connected between the output and input of said one amplifier.
Claim 3
Dependent Claim 18 words
The apparatus of claim 1 further characterized by and including an oscillator for periodically initiating said ramp signal.
Claim 4
Dependent Claim 14 words
The apparatus of claim 2 further characterized in that said oscillator includes a multivibrator.
Claim 5
Dependent Claim 17 words
The apparatus of claim 2 further characterized in that said first and second comparators include operational amplifiers.
Claim 6
Dependent Claim 24 words
The apparatus of claim 2 further characterized by and including reset and latching means connected between said multivibrator and said counting and display means.
Claim 7
Dependent Claim 22 words
The apparatus of claim 1 further characterized by and including overrange indicating means connected to said analog signal and said display means.
Claim 8
Dependent Claim 27 words
The apparatus of claim 6 further characterized in that said overrange indicating means includes an operational amplifier having inputs of said analog signal and a reference signal.
Claim 9
Dependent Claim 23 words
The apparatus of claim 7 further characterized in that said reference signal has a value above the normal value of said analog signal.
Claim 10
Dependent Claim 22 words
The apparatus of claim 1 further characterized by and including polarity indicating means connected to said analog signal and said display means.
Claim 11
Dependent Claim 28 words
The apparatus of claim 9 further characterized in that said polarity indicating means includes an operational amplifier having inputs of said analog signal and a negative reference signal.

References Cited (Backward Citations)

US3122729A Cited
US3303493A Cited
US3611131A Cited
US3742354A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-11-27 1982-05-29 1982-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-11-27 1986-05-29 1986-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-11-27 1990-05-29 1990-11-28 $7700.00 Window Closed / Lapsed

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