Data processing system self-test enabling technique

Claim 2

In a data processing system, a machine implemented process for enabling the self-test of a central processor included in the system when coupled with a main memory in the system, said central processor including a local memory for storing a plurality of test programs, said process comprising the method steps of: A. providing a first base address to one of said test programs stored in said local memory of said processor, said first base address being one of a plurality of base addresses, each of said base addresses used to address a different one of said test programs; B. providing a word address to the first word in said test program for which a said base address is provided by said step of providing; C. addressing a word location in a control store in said processor, said control store coupled to control the operation of said processor; D. determining that the contents of said word location addressed in said control store indicates that said local memory is to be addressed; E. addressing said local memory with said first base address and said word address; F. providing, independent of said step of addressing said local memory, a memory address to a word location in said main memory; G. transferring the contents of the word location addressed in said local memory to the word location indicated by said memory address; H. changing the value of the address of said word location in said local memory each time said step of transferring occurs; I. changing the value of the memory address of the word location in said main memory each time said step of transferring occurs; J. repeating said sequential steps of addressing, providing, transferring, changing and changing until said one of said test programs is stored in said main memory; and K. executing said one of said test programs to determine the performance level of said processor.

Claim 3

A process as in claim 1 wherein said step of repeating further comprises the steps of: A. determining whether each of the word locations in said local memory which is used to store said one of said test programs, have been addressed; B. entering said step of executing if each of said word locations used for storing said one of said test programs have been addressed; C. updating the addressing of both said local memory and said main memory if each of said word locations used for storing said one of said test programs have not been addressed; and D. repeating said steps of determining, entering and updating until all of said word locations used for storing said one of said test programs have been addressed.

Claim 4

A process as in claim 2 wherein said step of addressing said local memory with said word address is provided by means of counting means.

Claim 5

A process as in claim 3 wherein said step of determining whether each of the word locations used for storing said one of said test programs have been addressed includes the step of determining whether said counting means indicates a predetermined value.

Claim 6

A process as in claim 1 further comprising the step of initializing said processor and wherein said process commences in response to said step of initializing.

Claim 7

A process as in claim 1 further comprising the steps of: A. providing a second base address to another one of said test programs stored in said local memory; B. addressing with said second base address said another one of said test programs stored in said local memory; C. transferring said another one of said test programs to said main memory; and D. executing said another one of said test programs to determine yet a further performance level of said processor.

Claim 8

A data processing system including apparatus for enabling the self-test of a central processor included in the system when coupled with a main memory in the system, said central processor including a local memory for storing a plurality of test programs, said apparatus comprising: A. first means for providing a first base address to one of said test programs stored in said local memory of said processor, said first base address being one of a plurality of base addresses, each of said base addresses used to address a different one of said test programs; B. second means for providing a word address to the first word in said one of said test programs for which a said base address is provided by said first means for providing; C. means for addressing a word location in a control store in said processor, said control store coupled to control the operation of said processor; D. means for determining that the contents of said word location addressed in said control store indicates that said local memory is to be addressed; E. means for addressing said local memory with said first base address and said word address; F. means for providing a memory address to a word location in said main memory; G. means for transferring the contents of the word location addressed in said local memory to the word location indicated by said memory address; H. means for determining whether each of the word locations in said local memory which is used to store said one of said test programs, have been addressed; I. means for updating the addressing of both said local memory and said main memory if each of said word locations used for storing said one of said test programs have not been addressed; J. means for enabling said means for addressing, providing, transferring, determining and updating until said one of said test programs is stored in said main memory; and K. means for executing said one of said test programs to determine the performance level of said processor.

Claim 9

A data processing system including apparatus for enabling the self-test of a central processor included in the system when coupled with a main memory in the system, said central processor including a local memory for storing a plurality of test programs, said apparatus comprising: A. first means for providing a first base address to one of said test programs stored in said local memory of said processor, said first base address being one of a plurality of base addresses, each of said base addresses used to address a different one of said test programs; B. second means for providing a word address to the first word in said one of said test programs for which a said base address is provided by said first means for providing; C. means for addressing a word location in a control store in said processor, said control store coupled to control the operation of said processor; D. means for determining that the contents of said word location addressed in said control store indicates that said local memory is to be addressed; E. means for addressing said local memory with said first base address and said word address; F. means for providing a memory address to a word location in said main memory; G. means for transferring the contents of the word location addressed in said local memory to the word location indicated by said memory address; H. means for determining whether each of the word locations in said local memory which is used to store said one of said test programs, have been addressed; I. means for updating the addressing of both said local memory and said main memory if each of said word locations used for storing said one of said test programs have not been addressed; J. means for enabling said means for addressing, providing, transferring, determining and updating until said one of said test programs is stored in said main memory; and K. means for executing said one of said test programs to determine the performance level of said processor.

Claim 10

Apparatus as in claim 7 wherein said means for addressing said local memory includes means for counting and wherein said means for determining includes means for determining whether said means for counting indicates a predetermined value.