Memory overlay linking system

Claim 2

An overlay linking system for use in data processing applications, comprising: a main processor adapted to execute program instructions selected by a user and to produce address codes; a memory system connected to said main processor including a main memory having stored in uniquely addressable locations selectable by said address codes data or instruction codes and an accelerator memory for storing such ones of said data or instruction codes as are selected by ones of said address codes; overlay means disposed between said main and accelerator memories for advancing other ones of said data or instruction codes from said main memory to said accelerator memory in response to receiving other ones of said address codes or a link signal and for returning said ones of said data or instruction codes back to said main memory; and linking means including a random access memory having addressable fields connected for concurrent selection by said other ones of said address codes, each said field including a link code indicative of predetermined combination of sets of said other ones of said data or instruction codes for producing said link signal to said overlay means.

Claim 3

In a data processing system including a main processor producing address codes, a main memory having stored therein a plurality of data or instruction codes in uniquely addressable sets selectable by said address codes, an accelerator memory connected to communicate with said main processor having stored therein selected ones of said sets, and a memory control processor connected to said main and accelerator memories for periodically exchanging ones of said sets for other ones of said sets selected by said address codes between said main and accelerator memories, the improvement comprising: a programmable memory operatively connected to said main processor and including a plurality of corresponding uniquely addressable fields each said field being selected by said address code current with a corresponding one of said sets, each said field further including linking codes indicative of predetermined combination of said sets; and linking means connected to receive said link codes for controlling said memory control processor to select said other ones of said sets in said predetermined combinations, said memory control processor including a microprogram store, a program counter for advancing said microprogram store, overlay means controlled by said microprogram store and branch means connected to said program counter for modifying the advancement of said microprogram store according to said linking codes.

Claim 4

In a data processing system including a main processor producing address codes, a main memory having stored therein a plurality of data or instruction codes in uniquely addressable sets selectable by said address codes, an accelerator memory connected to communicate with said main processor having stored therein selected ones of said sets, and a memory control processor connected to said main and accelerator memories for periodically exchanging ones of said sets for other ones of said sets selected by said address codes between said main and accelerator memories, the improvement comprising: a programmable memory operatively connected to said main processor and including a plurality of corresponding uniquely addressable fields each said field being selected by said address code current with a corresponding one of said sets, each said field further including linking codes indicative of predetermined combination of said sets; and linking means connected to receive said link codes for controlling said memory control processor to select said other ones of said sets in said predetermined combinations, said memory control processor including a microprogram store, a program counter for advancing said microprogram store, overlay means controlled by said microprogram store and branch means connected to said program counter for modifying the advancement of said microprogram store according to said linking codes.

Claim 5

Apparatus according to claim 2 wherein: said programmable memory further includes status codes indicative of the presence of said sets in said accelerator memory said status codes being connected to initiate said program counter when a set addressed by said main processor is not in said accelerator memory.

Claim 6

Apparatus according to claim 3 wherein: said overlay means includes logic means for identifying said sets having the least recent usage from amongst said selected ones of said sets.

Claim 7

In a data processing system including a main memory storing data in page increments, each page being uniquely selectable by an address code, an accelerator memory, a processor conformed to execute programs and sequences and to produce said address codes according to said execution, and an overlay system connected between said main memory and said accelerator memory and adapted to receive said address codes for transferring from said main memory to said accelerator memory one of said page increments of data when said processor produces one of said address codes, the improvement comprising: linking means connected to receive said one address code from said processor and including a plurality of storage fields in sequential order, one of said fields being addressable by said one address code and other ones of said fields being addressable by other ones of said address code, each said field including one of a plurality of link codes, and advancing means connected between said main memory and said accelerator memory and adapted to receive said link codes in the other ones of said storage fields for overlaying other ones of said page increments when said binary codes in said other ones of said storage fields are equal to said binary code in said one storage field.

Claim 8

In a data processing system including a main memory storing data in page increments, each page being uniquely selectable by an address code, an accelerator memory, a processor conformed to execute programs and sequences and to produce said address codes according to said execution, and an overlay system connected between said main memory and said accelerator memory and adapted to receive said address codes for transferring from said main memory to said accelerator memory one of said page increments of data when said processor produces one of said address codes, the improvement comprising: linking means connected to receive said one address code from said processor and including a plurality of storage fields in sequential order, one of said fields being addressable by said one address code and other ones of said fields being addressable by other ones of said address code, each said field including one of a plurality of link codes, and advancing means connected between said main memory and said accelerator memory and adapted to receive said link codes in the other ones of said storage fields for overlaying other ones of said page increments when said binary codes in said other ones of said storage fields are equal to said binary code in said one storage field.

Claim 9

Apparatus according to claim 5 wherein: said advancing means includes sequencing means for selecting said other ones of said storage fields according to said sequential order thereof.