Patent US4126881A successfully refreshed from Google Patents.
US4126881A
Expired / Lapsed
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Semiconductor memory
Assignee: Siemens AG
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Filing: 1977-08-17
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Granted: 1978-11-21
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Expires: 1997-08-17
Abstract
Abstract A semiconductor memory has storage cells composed of MOS selector transistors operated by a drive line and storage capacitors connected to selector transistors. The selector transistors are constructed in accordance with the V-MOS technique. A semiconductor substrate is highly doped with atoms of one conductivity type and carries a buried layer highly doped with atoms of the opposite conductivity type. An epitaxial layer, weakly doped with atoms of the one conductivity type is carried over the buried layer and the semiconductor substrate. A second layer, highly doped with atoms of the opposite conductivity type, is carried over the epitaxial layer above the buried layer. A V-shaped groove divides the second layer into two sub-portions in the region of the storage cells and extends into the buried layer and a conductor path is disposed in the groove.
Inventors
- 👤 Paul-Werner von Basse
- 👤 Rudiger Hofmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/35; H; H10; H10B; H10B12/00; H10B12/30; H10B12/34; H10D; H10D30/00; H10D30/60; H10D30/63; H10D84/00; H10D84/80; H10D84/811; H10D84/813; Y; Y10; Y10S; Y10S257/00; Y10S257/911
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
A semiconductor memory comprising: a plurality of storage cells aligned in a row; a plurality of word lines, each of said word lines crossing a respective one of said storage cells, each of said storage cells including a pair of selector transistors and a storage capacitance formed and electrically connected to the respective word line by a structure comprising a semiconductor substrate highly doped with a dopant of one conductivity type, a buried layer in said substrate highly doped with a dopant of the opposite conductivity and with said substrate forming said storage capacitance, an epitaxial layer weakly doped with dopant of the one conductivity type carried over said buried layer and said substrate, a surface layer in the surface of said epitaxial layer over said buried layer of each of said memory cells, said surface layer being highly doped with dopant of the other conductivity type and forming a bit line, a V-shaped groove extending longitudinally of said storage cells and dividing said surface layer and thus said bit line into two sub-portions and extending through said epitaxial layer into said buried layer of each of said memory cells, an insulating layer carried over said epitaxial layer over said surface layer and over the surface of said groove, and a conductive path carried by said insulating layer over said buried layer and forming the respective word line.
Claim 2
Dependent Claim
228 words
A semiconductor memory comprising: a plurality of storage cells aligned in a row; a plurality of word lines, each of said word lines crossing a respective one of said storage cells, each of said storage cells including a pair of selector transistors and a storage capacitance formed and electrically connected to the respective word line by a structure comprising a semiconductor substrate highly doped with a dopant of one conductivity type, a buried layer in said substrate highly doped with a dopant of the opposite conductivity and with said substrate forming said storage capacitance, an epitaxial layer weakly doped with dopant of the one conductivity type carried over said buried layer and said substrate, a surface layer in the surface of said epitaxial layer over said buried layer of each of said memory cells, said surface layer being highly doped with dopant of the other conductivity type and forming a bit line, a V-shaped groove extending longitudinally of said storage cells and dividing said surface layer and thus said bit line into two sub-portions and extending through said epitaxial layer into said buried layer of each of said memory cells, an insulating layer carried over said epitaxial layer over said surface layer and over the surface of said groove, and a conductive path carried by said insulating layer over said buried layer and forming the respective word line.
Claim 3
Dependent Claim
21 words
The memory of claim 1, wherein said conductive path extends at right angles to said bit line and is insulated therefrom.
Claim 4
Dependent Claim
11 words
The memory of claim 2, wherein said conductive path comprises polysilicon.
Claim 5
Dependent Claim
23 words
The memory of claim 1, wherein a self-conducting layer is formed between said epitaxial layer, said buried layer and said surface layer sub-portions.
Claim 6
Dependent Claim
13 words
The memory of claim 1, wherein said buried layer is of spherical shape.
Claim 7
Dependent Claim
14 words
The memory of claim 1, wherein said buried layer is of approximately spherical shape.
References Cited (Backward Citations)
US4003036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-20 | 1982-05-22 | 1982-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-20 | 1986-05-22 | 1986-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-20 | 1990-05-22 | 1990-11-21 | $7700.00 | Window Closed / Lapsed |