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US4125933A
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IGFET Integrated circuit memory cell
Assignee: Samsung Electronics Co Ltd
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Filing: 1977-05-02
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Granted: 1978-11-21
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Expires: 1997-05-02
Abstract
Abstract An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps. A subsequent source and drain diffusion causes lateral migration of the conductive portions of the cell to increase the storage capacitance and to insure electrical contact between the island region of the capacitor and the source of the transfer transistor.
Inventors
- 👤 Steven M. Baldwin
- 👤 Donald L. Henderson, Sr.
- 👤 Joel A. Karp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:46
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10P30/21; H10P30/212; Y; Y10; Y10S; Y10S148/00; Y10S148/136; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
175 words
A method of making an enhanced semiconductor capacitor comprising the steps of: forming an insulating layer on a major surface of a semiconductor substrate, said substrate being of one conductivity type with a given impurity concentration; applying a maskant layer on the insulating layer; opening a window in the maskant layer; implanting impurity ions of said one conductivity type in said substrate surface through said window to form a region having the same conductivity type as said substrate yet having a greater impurity concentration than said substrate; implanting impurity ions of the opposite conductivity type and at a lower energy level than said ions of one said conductivity type into said region through the same window to form an island of opposite conductivity type within said region; removing said maskant layer; and forming a conductive field plate on said insulating layer and overlying said island; said region of said one conductivity type serving to increase the capacitance of the inversion layer associated with said island when a voltage is applied to said conductive field plate.
Claim 2
Independent Claim
175 words
A method of making an enhanced semiconductor capacitor comprising the steps of: forming an insulating layer on a major surface of a semiconductor substrate, said substrate being of one conductivity type with a given impurity concentration; applying a maskant layer on the insulating layer; opening a window in the maskant layer; implanting impurity ions of said one conductivity type in said substrate surface through said window to form a region having the same conductivity type as said substrate yet having a greater impurity concentration than said substrate; implanting impurity ions of the opposite conductivity type and at a lower energy level than said ions of one said conductivity type into said region through the same window to form an island of opposite conductivity type within said region; removing said maskant layer; and forming a conductive field plate on said insulating layer and overlying said island; said region of said one conductivity type serving to increase the capacitance of the inversion layer associated with said island when a voltage is applied to said conductive field plate.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the impurities of said region have a higher diffusion coefficient than the impurities of said island.
Claim 4
Dependent Claim
32 words
The method of claim 2 which further comprises the step of heating the substrate so that the impurities of said region diffuse laterally to wholely surround the lower portions of said island.
Claim 5
Dependent Claim
22 words
The method of claim 3 wherein the substrate and region have a P-type conductivity and wherein the island is of N-type conductivity.
Claim 6
Dependent Claim
26 words
The method of claim 4 wherein the impurity ions for said region are boron ions and wherein the impurity ions for said island are arsenic ions.
Claim 7
Dependent Claim
25 words
The method of claim 5 wherein the boron ions are implanted at a higher energy level than that at which the arsenic ions are implanted.
Claim 8
Independent Claim
295 words
A method of making a memory cell having an enhanced capacitor and a transfer transistor comprising the steps of: forming an insulating layer on the surface of a semiconductor substrate of one conductivity type with a given impurity concentration; forming a maskant layer over said insulating layer; opening a window in said maskant layer in regions wherein the capacitor is desired to be formed; implanting ions of said one conductivity type into said substrate surface through said window thereby forming a region in said substrate having a greater impurity concentration than the substrate; implanting through said same window impurity ions of the opposite conductivity type and at a lower energy than said ions of said one conductivity type to form an island within said region thereby forming a PN junction therebetween; removing the maskant layer; forming a second mask on said insulating layer having openings defining source and drain regions for a transfer transistor, with said source region opening being adjacent said island; diffusing impurity ions of said opposite conductivity type into said substrate surface to form said source and drain regions for the transfer transistor, the impurity ions of said source and island regions mutually laterally migrating so that said island and source region overlap to form a conductive connection therebetween, said region having a greater impurity concentration similarly laterally migrating to wholly surround lower portions of said island; forming a field plate on said insulating layer and overlying said island; and forming a gate region on said insulating layer and overlying portions of said substrate between said source and drain regions; said region having a greater impurity concentration than said substrate serving to increase the capacitance of the inversion layer associated with said island when a voltage is applied to said field plate.
Claim 9
Independent Claim
295 words
A method of making a memory cell having an enhanced capacitor and a transfer transistor comprising the steps of: forming an insulating layer on the surface of a semiconductor substrate of one conductivity type with a given impurity concentration; forming a maskant layer over said insulating layer; opening a window in said maskant layer in regions wherein the capacitor is desired to be formed; implanting ions of said one conductivity type into said substrate surface through said window thereby forming a region in said substrate having a greater impurity concentration than the substrate; implanting through said same window impurity ions of the opposite conductivity type and at a lower energy than said ions of said one conductivity type to form an island within said region thereby forming a PN junction therebetween; removing the maskant layer; forming a second mask on said insulating layer having openings defining source and drain regions for a transfer transistor, with said source region opening being adjacent said island; diffusing impurity ions of said opposite conductivity type into said substrate surface to form said source and drain regions for the transfer transistor, the impurity ions of said source and island regions mutually laterally migrating so that said island and source region overlap to form a conductive connection therebetween, said region having a greater impurity concentration similarly laterally migrating to wholly surround lower portions of said island; forming a field plate on said insulating layer and overlying said island; and forming a gate region on said insulating layer and overlying portions of said substrate between said source and drain regions; said region having a greater impurity concentration than said substrate serving to increase the capacitance of the inversion layer associated with said island when a voltage is applied to said field plate.
Claim 10
Dependent Claim
23 words
The method of claim 7 wherein the impurities of said capacitor region have a higher diffusion coefficient than the impurities of said island.
Claim 11
Independent Claim
241 words
A method of making an enhanced memory cell including a capacitor and transfer transistor comprising the steps: forming an oxide layer on the major surface of a P-type substrate having a given concentration; depositing a photoresist layer on said oxide layer; opening a window in said photoresist layer to define an area where the capacitor is to be formed; implanting boron ions through said window into said substrate surface to form a region having a greater impurity concentration than said substrate; implanting arsenic ions at a lower energy level than said boron ions through said same window into said region thereby forming an N-type island therein; removing said photoresist layer; depositing a polycrystalline silicon layer over the oxide layer; removing portions of said polycrystalline silicon layer to define a field plate overlying said N-type island and a gate region for an adjacent transfer transistor; and heating said substrate in a gaseous atmosphere of N-type impurities to diffuse said N-type impurites into said substrate surface to form source and drain regions for said transistor, said island region of said capacitor and the source region of the transistor laterally migrating and overlapping to provide a conductive connection therebetween, the impurities of said P+ region similarly laterally migrating during the heat of said diffusion to wholly surround lower portions of said island to thereby increase the capacitance of the inversion layer associated with said island when a voltage is applied to said field plate.
Claim 12
Independent Claim
241 words
A method of making an enhanced memory cell including a capacitor and transfer transistor comprising the steps: forming an oxide layer on the major surface of a P-type substrate having a given concentration; depositing a photoresist layer on said oxide layer; opening a window in said photoresist layer to define an area where the capacitor is to be formed; implanting boron ions through said window into said substrate surface to form a region having a greater impurity concentration than said substrate; implanting arsenic ions at a lower energy level than said boron ions through said same window into said region thereby forming an N-type island therein; removing said photoresist layer; depositing a polycrystalline silicon layer over the oxide layer; removing portions of said polycrystalline silicon layer to define a field plate overlying said N-type island and a gate region for an adjacent transfer transistor; and heating said substrate in a gaseous atmosphere of N-type impurities to diffuse said N-type impurites into said substrate surface to form source and drain regions for said transistor, said island region of said capacitor and the source region of the transistor laterally migrating and overlapping to provide a conductive connection therebetween, the impurities of said P+ region similarly laterally migrating during the heat of said diffusion to wholly surround lower portions of said island to thereby increase the capacitance of the inversion layer associated with said island when a voltage is applied to said field plate.
Claim 13
Dependent Claim
32 words
The method of claim 9 wherein boron ions are implanted at about 500 Kev to form said region and wherein arsenic ions are implanted at about 180 Kev to form said island.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-20 | 1982-05-22 | 1982-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-20 | 1986-05-22 | 1986-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-20 | 1990-05-22 | 1990-11-21 | $7700.00 | Window Closed / Lapsed |