Fault tolerant shift register type memory device

Claim 2

A shift register type memory device comprising a plurality of storage loops which store data and which have at least one alternative loop to be substituted for a defective loop, means to write data into said storage loops, a defective loop address memory which is constructed on the same storage medium as that of said storage loops and which stores a defective loop address in binary expression, a common detector which detects the information of said defective loop address memory and the data of said storage loops, a common propagation circuit which propagates the data read out from said defective loop address memory and said storage loops to said detector, and control means for rearranging the order of a pulse train of the data to be written by the data writing means or which has been read out by said detector on the basis of the defective loop address information detected by said detector to avoid the use of defective loops.

Claim 3

A shift register type memory according to claim 1, wherein said defective loop address memory is coupled to said common propagation circuit at a point which allows said common detector to read the data from said defective loop address memory prior to reading the data from said storage loops.

Claim 4

A shift register type memory device according to claim 1, wherein said storage medium is a magnetic substance, and said data and said information of said defective loop address memory are represented by magnetic bubbles.

Claim 5

A shift register type memory device according to claim 3, wherein said defective loop address memory consists of a plurality of closed loops, and an identical information is written into all bits of each of said loops.

Claim 6

A shift register type memory device according to claim 3, wherein said defective loop address memory consists of a plurality of idlers.

Claim 7

A shift register type memory device according to claim 3, wherein said defective loop address memory consists of a single closed loop.

Claim 8

A shift register type memory device according to claim 3, wherein said defective loop address memory is directly coupled with said propagation circuit.

Claim 9

A shift register type memory device according to claim 3, wherein said defective loop address memory is coupled through a separate propagation circuit for the defective loop address information with said common propagation circuit.

Claim 10

A shift register type memory device comprising a plurality of minor storage loops which store data including at least one alternative loop to be substituted for a defective loop, a major storage loop for propagating data read out from said minor storage loops and data to be read into said minor storage loops, input means connected to said major storage loop for writing data into said major storage loop, means for selectively gating data in parallel between said minor storage loops and said major storage loop, a defective loop address memory coupled to said major storage loop which is constructed on the same storage medium as that of said minor storage loops and which stores a defective loop address in binary expression, a common detector which detects the information of said defective loop address memory and the data of said minor storage loops gated through said major storage loop, and control means for rearranging the order of a pulse train of data to be written into said storage loops or which has been read out by said detector on the basis of the defective loop address information detected by said detector to avoid the use of defective loops.

Claim 11

A shift register type memory device comprising a plurality of minor storage loops which store data including at least one alternative loop to be substituted for a defective loop, a major storage loop for propagating data read out from said minor storage loops and data to be read into said minor storage loops, input means connected to said major storage loop for writing data into said major storage loop, means for selectively gating data in parallel between said minor storage loops and said major storage loop, a defective loop address memory coupled to said major storage loop which is constructed on the same storage medium as that of said minor storage loops and which stores a defective loop address in binary expression, a common detector which detects the information of said defective loop address memory and the data of said minor storage loops gated through said major storage loop, and control means for rearranging the order of a pulse train of data to be written into said storage loops or which has been read out by said detector on the basis of the defective loop address information detected by said detector to avoid the use of defective loops.

Claim 12

A shift register type memory device according to claim 9 wherein said control means is connected to the input of said input means and the output of said detector to operate on the pulse train applied to said input means and the pulse train derived from said detector.

Claim 13

A shift register type memory device according to claim 9 wherein said control means includes at least one delay element to which said pulse train is applied and counter means responsive to said defective loop address information for selectively outputting said pulse train from the output of said delay element or bypassing said delay element.

Claim 14

A shift register type memory device according to claim 11 wherein said minor storage loops include a plurality of alternative loops and said control means includes a number of delay elements equal to the number of alternative loops.