US4125789A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Biasing and scaling circuit for transducers
Assignee: Honeywell International Inc
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Filing: 1977-06-07
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Granted: 1978-11-14
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Expires: 1997-06-07
Abstract
Abstract In order to provide a substantially error free biasing and scaling circuit for transducer signals, an operational amplifier and a field effect transistor are used in combination with a DC voltage source to bias and scale the transducer signal.
Inventors
- 👤 Michael M. Van Schoiack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:41
CPC Classifications
G; G01; G01D; G01D3/00; G01D3/06; G01D5/00; G01D5/12; G01P; G01P15/00; G01P15/02; G01P15/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
127 words
A bias and scaling circuit for use with a source of signals from a transducer or the like comprising: a voltage source; an operational amplifier having a first and a second input terminal and an output terminal; a diode connected between said voltage source and said first operational amplifier input terminal; a current summing junction connected to said second operational amplifier input; a bias resistor connected between said voltage source and said current summing junction; a scaling resistor connected between the signal source and said current summing junction; a field effect transistor having a gate terminal connected to said operational amplifier output terminal and an input terminal connected to said current summing junction; and a load resistor connected to an output terminal of said field effect transistor.
Claim 2
Dependent Claim
127 words
A bias and scaling circuit for use with a source of signals from a transducer or the like comprising: a voltage source; an operational amplifier having a first and a second input terminal and an output terminal; a diode connected between said voltage source and said first operational amplifier input terminal; a current summing junction connected to said second operational amplifier input; a bias resistor connected between said voltage source and said current summing junction; a scaling resistor connected between the signal source and said current summing junction; a field effect transistor having a gate terminal connected to said operational amplifier output terminal and an input terminal connected to said current summing junction; and a load resistor connected to an output terminal of said field effect transistor.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 wherein said voltage source is a source of positive direct current.
Claim 4
Dependent Claim
12 words
The circuit of claim 1 wherein said diode is a zener diode.
Claim 5
Dependent Claim
27 words
The circuit of claim 2 wherein: said first operation amplifier input terminal is a negative terminal; and said second operational amplifier input terminal is a positive terminal.
Claim 6
Dependent Claim
16 words
The circuit of claim 4 wherein said field effect transistor is an N-channel field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-13 | 1982-05-15 | 1982-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-13 | 1986-05-15 | 1986-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-13 | 1990-05-15 | 1990-11-14 | $7700.00 | Window Closed / Lapsed |