Method and apparatus for signaling and framing in a time division multiplex communication system

Claim 2

In a frame-organized time division multiplex system wherein each frame comprises a plurality of multibit information channels and at least one additional bit, and wherein predetermined frames are used to substitute signaling information in at least one predetermined bit position of each multibit information channel, a method for utilizing said at least one additional bit for providing combined frame synchronization and reframing, frame identification of said predetermined frames, and common channel signaling, said method comprising the steps of: (a) generating in said at least one additional bit position of the even-numbered frames a repetitive bit pattern suitable for identifying said predetermined frames, (b) generating a frame synchronization status signal by monitoring successive received signal states in said at least one additional bit position of said even-numbered frames, (c) reframing by monitoring for the presence of said repetitive bit pattern whenever said status signal indicates absence of frame synchronization, and (d) performing common channel signaling in said at least one additional bit position of the odd-numbered frames whenever said status signal indicates presence of frame synchronization.

Claim 3

A method as set forth in claim 1, wherein said predetermined frames comprise every sixth and twelfth frame, and wherein said at least one predetermined bit position comprises the least significant bit position of each channel of said predetermined frames.

Claim 4

A method as set forth in claim 2, wherein said repetitive bit pattern comprises the binary sequence 000111.

Claim 5

A method as set forth in claim 2, wherein said repetitive bit pattern comprises the binary sequence 000101.

Claim 6

In a frame-organized time division multiplex system including information sending and receiving means, wherein each frame comprises a plurality of multibit information channels and at least one additional bit, and wherein predetermined frames are used to substitute signaling information in at least one predetermined bit position of each multibit information channel, apparatus for effecting combined frame synchronization and reframing, identification of said predetermined frames, and common channel signaling, said apparatus comprising; means, coupled to said information sending means, for generating in said at least one additional bit position of consecutive even-numbered frames a repetitive bit pattern suitable for use in identifying said predetermined frames, framing means having an input coupled to said information receiving means, including detection means for examining each bit position of consecutive pairs of frames for the occurrence of said repetitive bit pattern, framing control means coupled to said detection means operative to generate a first synchronization status signal whenever said repetitive bit pattern is detected in said at least one additional bit position of consecutive even-numbered frames and to generate a second synchronization status signal whenever said repetitive bit pattern is not so detected, said framing control means further operative to monitor for the subsequent reoccurrence of said repetitive bit pattern in one, and only one, bit position of said consecutive even-numbered frames whenever said second status signal is generated, and common channel signaling means, coupled to said framing means and to said sending means, operative to insert signaling information into said at least one additional bit position of the odd-numbered frames sent by said sending means whenever said first status signal is generated.

Claim 7

In a frame-organized time division multiplex system including information sending and receiving means, wherein each frame comprises a plurality of multibit information channels and at least one additional bit, and wherein predetermined frames are used to substitute signaling information in at least one predetermined bit position of each multibit information channel, apparatus for effecting combined frame synchronization and reframing, identification of said predetermined frames, and common channel signaling, said apparatus comprising; means, coupled to said information sending means, for generating in said at least one additional bit position of consecutive even-numbered frames a repetitive bit pattern suitable for use in identifying said predetermined frames, framing means having an input coupled to said information receiving means, including detection means for examining each bit position of consecutive pairs of frames for the occurrence of said repetitive bit pattern, framing control means coupled to said detection means operative to generate a first synchronization status signal whenever said repetitive bit pattern is detected in said at least one additional bit position of consecutive even-numbered frames and to generate a second synchronization status signal whenever said repetitive bit pattern is not so detected, said framing control means further operative to monitor for the subsequent reoccurrence of said repetitive bit pattern in one, and only one, bit position of said consecutive even-numbered frames whenever said second status signal is generated, and common channel signaling means, coupled to said framing means and to said sending means, operative to insert signaling information into said at least one additional bit position of the odd-numbered frames sent by said sending means whenever said first status signal is generated.

Claim 8

Apparatus as set forth in claim 5 wherein said predetermined frames comprise every sixth and twelfth frame, and wherein said at least one predetermined bit position comprises the least significant bit position of each channel of said predetermined frame.

Claim 9

Apparatus as set forth in claim 6 wherein said repetitive bit pattern comprises the binary sequence 000111.

Claim 10

Apparatus as set forth in claim 6 wherein said repetitive bit pattern comprises the binary sequence 000101.

Claim 11

Apparatus as set forth in claim 5 wherein said detection means further comprises; history memory means coupled to said framing means input, including at least a plurality of individually addressable memory locations equal to the total number of bit positions of a pair of consecutively received frames, each of said memory locations having capacity to store signal values received in the corresponding frame bit position for a predetermined number of previously received frames, means for reading any of said memory locations and placing the results on said predetermined number of history memory means outputs, and combinational logic means having inputs coupled to said history memory means outputs and to said framing means input, operative during each received frame bit position to generate at the detection means output a first violation signal whenever the concatenated signal values from said history memory means outputs along with the signal value for the bit position currently being received do not correspond to a valid subsequence of said repetitive bit pattern.

Claim 12

Apparatus as set forth in claim 9 wherein said framing control means further comprises; violation history memory means for storing a plurality of indicator bit each corresponding to a bit position of the pair of consecutively received frames whose history bit signal values are stored in said history memory means, a sequential state logic machine having a first output coupled to means for writing into said violation history memory means and a second output for indicating the presence of said first and second synchronization status signals, said second output coupled to a first input of said sequential state logic machine, a combinational logic element having a first input coupled to said detection means output and a second input coupled to means for reading out the contents of any location of said violation history memory means, said logic element operative to logically OR the signals appearing on its first and second inputs to an element output coupled to a second input of said sequential state logic machine; whereby said sequential state logic machine is operative as connected to examine only said at least one additional bit position of even-numbered frames for the presence of said repetitive bit pattern whenever said first synchronization status signal is generated and to examine every frame bit position in conjunction with said history memory means and said violation history memory means for said repetitive bit pattern whenever said second synchronization status signal is generated.

Claim 13

Apparatus as set forth in claim 10 wherein the combinational logic portion of said sequential state logic machine comprises a read-only memory means programmed to provide a plurality of logic states suitable for use in detecting with transient filtering the loss of frame synchronization in said at least one additional bit of even-numbered frames and for use in searching for the reoccurrence of said repetitive bit pattern in one, and only one, bit position of said even-numbered frames for a predetermined confidence time interval whenever loss of frame synchronization is indicated by said second synchronization status signal.