Patent US4124900A successfully refreshed from Google Patents.
US4124900A
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Memory using interleaved rows to permit closer spacing
Assignee: Micron Technology Inc
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Filing: 1977-09-29
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Granted: 1978-11-07
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Expires: 1997-09-29
Abstract
Abstract An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
Inventors
- 👤 Philip C. Smith
- 👤 John L. Fagan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:11
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C11/00; G11C11/21; G11C11/26; G11C11/30; G11C16/04; G11C16/0466; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/10; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
213 words
an electrically alterable non-volatile memory for storing information comprising: a substrate, an array of electrically alterable non-volatile memory elements arranged in a number of rows in a predetermined area on said substrate, said rows being colinear and parallel to one another and extending to a first and second side of said area, a first group of at least two rows interleaved between a second group of at least 3 rows, said memory elements of each row of said first and second groups coupled to a conductor running along each row, first decode logic coupled to said conductors of said first group of rows on said first side of said area for selecting one of said rows in response to a number of predetermined addresses, second decode logic coupled to said conductors of said second group of rows on said second side of said area for selecting one of said rows in response to a number of predetermined addresses, and means coupled to said array of memory elements for clearing said array of memory elements to a first predetermined threshold voltage, means coupled to said array of memory elements for writing selected memory elements to a second predetermined threshold voltage, and means coupled to said array of memory elements for reading selected memory elements.
Claim 2
Dependent Claim
213 words
an electrically alterable non-volatile memory for storing information comprising: a substrate, an array of electrically alterable non-volatile memory elements arranged in a number of rows in a predetermined area on said substrate, said rows being colinear and parallel to one another and extending to a first and second side of said area, a first group of at least two rows interleaved between a second group of at least 3 rows, said memory elements of each row of said first and second groups coupled to a conductor running along each row, first decode logic coupled to said conductors of said first group of rows on said first side of said area for selecting one of said rows in response to a number of predetermined addresses, second decode logic coupled to said conductors of said second group of rows on said second side of said area for selecting one of said rows in response to a number of predetermined addresses, and means coupled to said array of memory elements for clearing said array of memory elements to a first predetermined threshold voltage, means coupled to said array of memory elements for writing selected memory elements to a second predetermined threshold voltage, and means coupled to said array of memory elements for reading selected memory elements.
Claim 3
Dependent Claim
24 words
The electrically alterable non-volatile memory of claim 1 wherein said memory element is a variable threshold transistor having a gate, source and drain electrode.
References Cited (Backward Citations)
US3965462A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-06 | 1982-05-08 | 1982-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-06 | 1986-05-08 | 1986-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-06 | 1990-05-08 | 1990-11-07 | $7700.00 | Window Closed / Lapsed |