US4123726A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for synchronizing the oscillation of an oscillator keyed by a pulse, with a reference oscillation
Assignee: Siemens AG
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Filing: 1977-09-15
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Granted: 1978-10-31
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Expires: 1997-09-15
Abstract
Abstract A circuit for synchronizing an oscillator keyed by a pulse is provided with a low amplitude reference oscillation. A phase shift regulating loop has a phase discriminator which is fed, on one hand, with a branched component of the oscillator output and, on the other hand, with the reference oscillation. The phase discriminator compares the phases of the two oscillators and emits a resultant regulating voltage an adjustable reactance for controlling the oscillator frequency during the leading edge of the keying pulse. A phase shift device, adjustable over 180°, is connected between the oscillator and the phase discriminator, the phase discriminator having a high-ohmic output which is connected, via an impedance converter, to the adjustable reactance. A sampling switch is interposed between the impedance converter and the adjustable reactance, the switch being closed at the beginning of a pulse and opened shortly before the end of a pulse, the pulses being of predetermined duration, and a holding circuit holds the regulating voltage at least to an approximate value across the adjustable reactance prior to the end of a pulse, until the closing of the sampling switch.
Inventors
- 👤 Peter Schucht
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:36
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/18; H03B5/1841; H03B5/1847; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/083; H03L7/14; H03L7/24; H03B2200/00; H03B2200/003; H03B2200/004; H03B2201/00; H03B2201/02; H03B2201/0208
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
195 words
A synchronization circuit for an oscillator keyed by a keying pulse, with a low amplitude reference oscillation which is input coupled to the oscillator, comprising: a phase regulating loop including a phase discriminator connected to receive the output oscillations of the oscillator and the reference oscillation and to compare the phase states thereof and produce a resultant regulating voltage, said phase discriminator including a high impedance output; an adjustable reactance connected to the oscillator and to said phase discriminator for controlling the output frequency of the oscillator in accordance with said regulating voltage; a phase shift device which is adjustable up to 180° connected between the oscillator and said phase discriminator; an impedance converter connecting said high impedance output of said phase discriminator in a low impedance fashion to said adjustable reactance; a sampling switch serially interposed between said adjustable reactance, said sampling switch connected to receive and respond to the keying pulse and close for a duration less than the pulse duration; and a holding circuit for holding the regulating voltage across said adjustable reactance from a time prior to the end of a keying pulse until the next closure of said sampling switch.
Claim 2
Dependent Claim
195 words
A synchronization circuit for an oscillator keyed by a keying pulse, with a low amplitude reference oscillation which is input coupled to the oscillator, comprising: a phase regulating loop including a phase discriminator connected to receive the output oscillations of the oscillator and the reference oscillation and to compare the phase states thereof and produce a resultant regulating voltage, said phase discriminator including a high impedance output; an adjustable reactance connected to the oscillator and to said phase discriminator for controlling the output frequency of the oscillator in accordance with said regulating voltage; a phase shift device which is adjustable up to 180° connected between the oscillator and said phase discriminator; an impedance converter connecting said high impedance output of said phase discriminator in a low impedance fashion to said adjustable reactance; a sampling switch serially interposed between said adjustable reactance, said sampling switch connected to receive and respond to the keying pulse and close for a duration less than the pulse duration; and a holding circuit for holding the regulating voltage across said adjustable reactance from a time prior to the end of a keying pulse until the next closure of said sampling switch.
Claim 3
Dependent Claim
19 words
The circuit of claim 1, wherein said sampling switch comprises: a field effect transistor as a high-speed switch-through element.
Claim 4
Dependent Claim
22 words
The circuit of claim 2, and further comprising: a capacitor connected in parallel with the switch-through path of said field effect transistor.
Claim 5
Dependent Claim
12 words
The circuit of claim 3, wherein said capacitor is a trimmer capacitor.
Claim 6
Dependent Claim
31 words
The circuit of claim 2, and further comprising: a capacitor and a resistor connected in parallel with each other and in series with the switch-through path of said field effect transistor.
Claim 7
Dependent Claim
100 words
The circuit of claim 1, comprising: a modulator connected to said sampling switch and including an input for receiving the keying pulses, a first monostable multivibrator connected to said input and to said sampling switch, said first multivibrator triggered by the leading edge of a keying pulse to close said sampling switch, said first multivibrator having a short fall time, and a second monostable multivibrator connected between said input and said sampling switch, said second multivibrator reset by the leading edge of a keying pulse and triggered by the trailing edge of a keying pulse to open said sampling switch.
Claim 8
Dependent Claim
38 words
The circuit of claim 6, wherein said sampling switch comprises a field effect transistor including a gate and a switch-through path, and said circuit further comprises: gating means connected between said first and second multivibrators and said gate.
Claim 9
Dependent Claim
13 words
The circuit of claim 7, wherein said gating means comprises an AND gate.
Claim 10
Dependent Claim
13 words
The circuit of claim 7, wherein said gating means comprises a NAND gate.
Claim 11
Dependent Claim
13 words
The circuit of claim 1, wherein said impedance converter comprises a video amplifier.
Claim 12
Dependent Claim
15 words
The circuit of claim 1, wherein said holding circuit is formed by said adjustable reactance.
Claim 13
Dependent Claim
24 words
The circuit of claim 1, wherein said holding circuit comprises a field effect transistor and a charging capacitor connected to said field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-30 | 1982-05-01 | 1982-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-30 | 1986-05-01 | 1986-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-30 | 1990-05-01 | 1990-10-31 | $7700.00 | Window Closed / Lapsed |