Patent US4123300A successfully refreshed from Google Patents.
US4123300A
Expired / Lapsed
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Integrated circuit process utilizing lift-off techniques
Assignee: International Business Machines Corp
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Filing: 1977-05-02
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Granted: 1978-10-31
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Expires: 1997-05-02
Abstract
Abstract A method for making high density integrated circuits which utilizes lift-off techniques provides a structure having a single layer of insulating material for both the dielectric of a storage capacitor and the insulator for a gate or control electrode of a switching element. The steps of the method include forming a thin layer of silicon dioxide on a silicon substrate followed by a layer of first doped polysilicon and, optionally, a layer of silicon nitride and then a layer of photoresist. The layers are etched to the silicon dioxide surface with the exception of the portion of the layers overlying a region defined as the gate or control electrode of the switching element. A second layer of doped polysilicon is then deposited over the remaining structure to provide on the silicon dioxide layer a second conductive layer adjacent to but spaced from the first polysilicon layer forming the gate or control electrode. The silicon nitride, when used, is etched away and a strip of conductive metal is placed in contact with the first conductive polysilicon layer after the second doped polysilicon layer has been appropriately oxidized to form an insulating medium over this second polysilicon layer and between the first and second polysilicon layers. Any desired n+ regions may be formed in the silicon substrate by diffusing impurities into the substrate prior to forming the silicon dioxide layer, or the n+ regions may be formed after the silicon dioxide has been formed by using appropriate ion implantation techniques. By employing this method, high density one device memory arrays may be produced by using the first doped polysilicon layer for forming the gate electrode of a field effect transistor and the second doped polysilicon layer as an electrode of the storage capacitor.
Inventors
- 👤 Madhukar L. Joshi
- 👤 Paul F. Landler
- 👤 Ronald Silverman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:11
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
154 words
A method of making an integrated circuit in a semiconductor comprising the steps of forming a dielectric layer on the semiconductor surface; depositing a first layer of polycrystalline silicon on said dielectric layer; superimposing on said silicon layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a protected region of said first layer of polycrystalline silicon; removing that portion of said first polycrystalline silicon layer without said protected region; depositing a second layer of polycrystalline silicon over said dielectric layer without the edges of said patterned layer of photoresist and over said patterned photoresist layer; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; and oxidizing the surfaces of the remaining portions of said first and second polycrystalline silicon layers to form insulated polycrystalline silicon segments in proximity to each other on said dielectric layer.
Claim 2
Independent Claim
154 words
A method of making an integrated circuit in a semiconductor comprising the steps of forming a dielectric layer on the semiconductor surface; depositing a first layer of polycrystalline silicon on said dielectric layer; superimposing on said silicon layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a protected region of said first layer of polycrystalline silicon; removing that portion of said first polycrystalline silicon layer without said protected region; depositing a second layer of polycrystalline silicon over said dielectric layer without the edges of said patterned layer of photoresist and over said patterned photoresist layer; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; and oxidizing the surfaces of the remaining portions of said first and second polycrystalline silicon layers to form insulated polycrystalline silicon segments in proximity to each other on said dielectric layer.
Claim 3
Dependent Claim
36 words
A method of making an integrated circuit in a semiconductor as set forth in claim 1 wherein said portion of said first layer of polycrystalline silicon without said protected region is removed by an etching process.
Claim 4
Dependent Claim
56 words
A method of making an integrated circuit in a semiconductor as set forth in claim 1 wherein said semiconductor has a given conductivity and further comprising the step of introducing an impurity into said semiconductor so as to provide a first region adjacent said protected region having a conductivity opposite to that of said given conductivity.
Claim 5
Dependent Claim
39 words
A method of making an integrated circuit in a semiconductor as set forth in claim 1 further including the step of interposing a layer of silicon nitride between said first layer of polycrystalline silicon and said patterned photoresist layer.
Claim 6
Dependent Claim
33 words
A method of making an integrated circuit in a semiconductor as set forth in claim 2 wherein said portion of said first polycrystalline layer without said protected region is removed in its entirety.
Claim 7
Dependent Claim
50 words
A method of making an integrated circuit in a semiconductor as set forth in claim 1 wherein said portion of said first polycrystalline layer without said protected region is removed partially so as to form a region of said first polycrystalline silicon layer thinner than that of said protected region.
Claim 8
Dependent Claim
52 words
A method of making an integrated circuit in a semiconductor as set forth in claim 3 further comprising the step of introducing said impurity into said semiconductor so as to provide first and second regions on opposite sides of said protected region having a conductivity opposite to that of said given conductivity.
Claim 9
Dependent Claim
77 words
A method of making an integrated circuit in a semiconductor as set forth in claim 4 further including the steps of interposing first and second silicon dioxide layers between said first layer of polycrystalline silicon and said patterned photoresist layer, said first silicon dioxide layer being disposed between said first layer of polycrystalline silicon and said silicon nitride layer and said second silicon dioxide layer being disposed between said silicon nitride layer and said patterned photoresist layer.
Claim 10
Dependent Claim
37 words
A method of making an integrated circuit in a semiconductor as set forth in claim 4 further including the step of removing said layer of silicon nitride to expose a surface of said first polycrystalline silicon layer.
Claim 11
Dependent Claim
56 words
A method of making an integrated circuit in a semiconductor as set forth in claim 7 wherein one of said first and second regions is defined by said patterned photoresist layer and a second photoresist layer, one of said photoresist layers being a positive photoresist and the other of said photoresist layers being a negative photoresist.
Claim 12
Dependent Claim
40 words
A method of making an integrated circuit in a semiconductor as set forth in claim 7 further including forming an insulator over one of said first and second regions to a thickness substantially greater than that of said dielectric layer.
Claim 13
Dependent Claim
29 words
A method of making an integrated circuit in a semiconductor as set forth in claim 9 wherein said silicon nitride layer is removed by an unmasked dip etch process.
Claim 14
Independent Claim
150 words
A method of making an integrated circuit on a substrate comprising the steps of: depositing a first layer of polycrystalline silicon on said substrate; superimposing on said silicon layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a protected region of said first layer of polycrystalline silicon; removing a portion of said first polycrystalline silicon layer without said protected region; depositing a second layer of polycrystalline silicon over said substrate without the edges of said patterned layer of photoresist and over said patterned photoresist layer; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; and oxidizing the surfaces of the remaining portions of said first and second polycrystalline silicon layers to form polycrystalline silicon segments on said substrate insulated from each other without one of said silicon layers overlapping the other.
Claim 15
Independent Claim
150 words
A method of making an integrated circuit on a substrate comprising the steps of: depositing a first layer of polycrystalline silicon on said substrate; superimposing on said silicon layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a protected region of said first layer of polycrystalline silicon; removing a portion of said first polycrystalline silicon layer without said protected region; depositing a second layer of polycrystalline silicon over said substrate without the edges of said patterned layer of photoresist and over said patterned photoresist layer; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; and oxidizing the surfaces of the remaining portions of said first and second polycrystalline silicon layers to form polycrystalline silicon segments on said substrate insulated from each other without one of said silicon layers overlapping the other.
Claim 16
Independent Claim
217 words
A method of making a memory circuit in a semiconductor comprising the steps of forming source and drain electrodes in said semiconductor; forming a dielectric layer on said semiconductor; depositing a first layer of doped polycrystalline silicon on said dielectric layer; depositing a layer of silicon nitride on said first layer of polycrystalline silicon; forming on said silicon nitride layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a gate region between said source and drain electrodes; removing portions of said silicon nitride layer and said first layer of doped polycrystalline silicon without said gate region; depositing a second layer of doped polycrystalline silicon over said dielectric layer without the edges of said patterned layer of photoresist and over said patterned layer of photoresist; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; oxidizing portions of said first and second polycrystalline silicon layers to form polycrystalline silicon segments insulated from each other; removing the remaining portion of said layer of silicon nitride to expose a surface of said first polycrystalline silicon layer; and depositing a conductive line over said first and second polycrystalline silicon layers in electrical contact with said exposed surface of said first polycrystalline silicon layer.
Claim 17
Independent Claim
217 words
A method of making a memory circuit in a semiconductor comprising the steps of forming source and drain electrodes in said semiconductor; forming a dielectric layer on said semiconductor; depositing a first layer of doped polycrystalline silicon on said dielectric layer; depositing a layer of silicon nitride on said first layer of polycrystalline silicon; forming on said silicon nitride layer a patterned layer of photoresist defining within the edges of said patterned layer of photoresist a gate region between said source and drain electrodes; removing portions of said silicon nitride layer and said first layer of doped polycrystalline silicon without said gate region; depositing a second layer of doped polycrystalline silicon over said dielectric layer without the edges of said patterned layer of photoresist and over said patterned layer of photoresist; removing said patterned photoresist layer and that portion of said second layer of polycrystalline silicon deposited over said patterned photoresist layer; oxidizing portions of said first and second polycrystalline silicon layers to form polycrystalline silicon segments insulated from each other; removing the remaining portion of said layer of silicon nitride to expose a surface of said first polycrystalline silicon layer; and depositing a conductive line over said first and second polycrystalline silicon layers in electrical contact with said exposed surface of said first polycrystalline silicon layer.
Claim 18
Dependent Claim
40 words
A method of making a memory circuit as set forth in claim 14 further comprising the step of forming an insulator over one of said source and drain electrodes to a thickness substantially greater than that of said dielectric layer.
References Cited (Backward Citations)
US4055885A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-30 | 1982-05-01 | 1982-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-30 | 1986-05-01 | 1986-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-30 | 1990-05-01 | 1990-10-31 | $7700.00 | Window Closed / Lapsed |