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US4122441A
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Error detection and indication system for bi-phase encoded digital data
Assignee: Lockheed Electronics Co Inc
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Filing: 1977-10-05
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Granted: 1978-10-24
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Expires: 1997-10-05
Abstract
Abstract A real-time error detection system for bi-phase or similarly encoded digital data is disclosed. Bi-phase or similarly encoded data, which utilizes two transitions in a bit cell for either a binary "1" or a binary "0" value, and one transition in a bit cell for the other binary value inherently generates an even number of transitions of the binary value represented by the two transitions between the occurrence of the other binary value represented by one transition. Monitoring for the number of transitions of the binary value represented by two transitions provides an indication of the occurrence of an odd number of transitions. This represents an error condition. The system utilizes a logic circuit responsive to the binary "1" and binary "0" data clock retrieved from the self-clocking bi-phase encoded data. When an error condition is detected, an error indicating signal is generated.
Inventors
- 👤 Robert Lee Robinson
- 👤 David Casper Hoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:48
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
107 words
A real-time error detection system for bi-phase or similarly encoded binary data wherein a binary "1" and binary "0" clock signal is generated during the decoding of said data, said error detection system comprising: means for storing the transitions of the binary values (either "1" or "0") which are represented by an even number of transitions per bit cell; means for interrogating said storing means upon the occurrence of the other binary values (either "1" or "0") which are represented by an odd number of transitions per bit cell; and means for indicating an error if said storing means contains an odd number of transitions when interrogated.
Claim 2
Dependent Claim
107 words
A real-time error detection system for bi-phase or similarly encoded binary data wherein a binary "1" and binary "0" clock signal is generated during the decoding of said data, said error detection system comprising: means for storing the transitions of the binary values (either "1" or "0") which are represented by an even number of transitions per bit cell; means for interrogating said storing means upon the occurrence of the other binary values (either "1" or "0") which are represented by an odd number of transitions per bit cell; and means for indicating an error if said storing means contains an odd number of transitions when interrogated.
Claim 3
Dependent Claim
27 words
The real-time error detection system of claim 1 further comprising: means for generating an error count signal each time an error is indicated by said indicating means.
Claim 4
Dependent Claim
26 words
The real-time error detection system of claim 1 wherein said storing means comprises a D-type flip-flop which receives the binary "1" clock at its clock input.
Claim 5
Dependent Claim
37 words
The real-time error detection system of claim 3 wherein said interrogating means comprises a dual input gate which receives the binary "0" clock at one input and the output of said D-type flip-flop at the other input.
Claim 6
Dependent Claim
26 words
The real-time error detection system of claim 4 wherein the output of said dual input gate is connected to a reset input of sad D-type flip-flop.
Claim 7
Dependent Claim
28 words
The real-time error detection system of claim 5 wherein said indicating means comprises a one-shot multi-vibrator receiving the output of said dual input gate at its triggering input.
Claim 8
Dependent Claim
22 words
The real-time error detection system of claim 5 wherein the Q output of said D-type flip-flop is connected to its D input.
Claim 9
Dependent Claim
18 words
The real-time error detection system of claim 1 wherein said storing means receives the binary "1" clock signals.
Claim 10
Dependent Claim
18 words
The real-time error detection system of claim 8 wherein said interrogating means receives the binary "0" clock signals.
Claim 11
Dependent Claim
18 words
The real-time error detection system of claim 1 wherein said storing means receives the binary "0" clock signals.
Claim 12
Dependent Claim
18 words
The real-time error detection system of claim 10 wherein said interrogating means receives the binary "1" clock signals.
Claim 13
Dependent Claim
16 words
The real-time error detection system of claim 11 wherein said storing means comprises a D-type flip-flop.
Claim 14
Dependent Claim
37 words
The real-time error detection system of claim 12 wherein said interrogating means comprises a dual input gate which receives the binary "1" clock at one input and the output of said D-type flip-flop at the other input.
Claim 15
Dependent Claim
131 words
A real-time error detection system for bi-phase or similarly encoded binary data wherein a binary "1" and binary "0" clock signal is generated during the decoding of said data, said error detection system comprising: a D-type flip-flop receiving the binary "1" clock signal at its clock input, its Q output being connected to its D input; a two input NAND gate receiving the binary "0" clock at one input and the Q output of said D-type flip-flop at its other input, the output of the NAND gate being connected to the reset input of said D-type flip-flop; and a one-shot multi-vibrator receiving the output of said NAND gate at its triggering input, said multi-vibrator generating an error indicating signal having a duration dependent on the RC time constant of said multi-vibrator.
Claim 16
Dependent Claim
131 words
A real-time error detection system for bi-phase or similarly encoded binary data wherein a binary "1" and binary "0" clock signal is generated during the decoding of said data, said error detection system comprising: a D-type flip-flop receiving the binary "1" clock signal at its clock input, its Q output being connected to its D input; a two input NAND gate receiving the binary "0" clock at one input and the Q output of said D-type flip-flop at its other input, the output of the NAND gate being connected to the reset input of said D-type flip-flop; and a one-shot multi-vibrator receiving the output of said NAND gate at its triggering input, said multi-vibrator generating an error indicating signal having a duration dependent on the RC time constant of said multi-vibrator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |