US4122311A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic multiplexer for parallel, bi-directional scanning thermal imaging system
Assignee: Raytheon Co
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Filing: 1977-10-13
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Granted: 1978-10-24
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Expires: 1997-10-13
Abstract
Abstract A system for generating a serial video signal from a plurality of parallel channels particularly useful in thermal imaging systems incorporating bi-directional scanning. Signals on parallel input lines are simultaneously sampled and held by individual sample and hold circuits in each channel. A first multiplex level having a plurality of slow multiplexers is arranged so that each slow multiplexer selects a subset of the total number of analog inputs to generate a serial output from each slow multiplexer. Each such single output is coupled to a high speed gate in a fast multiplexer to generate a serial output from a single output channel. The fast multiplexers operate at a rate determined by the output scan time divided by the number of parallel input channels. The slow multiplexers operate at a fraction of this speed where the fraction is equivalent to one over the number of slow multiplexers generating an input to the fast multiplexer.
Inventors
- 👤 Robert W. Klatt
- 👤 Preben B. Jensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:58
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H04L; H04L5/00; H04L5/22
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
274 words
A multiplexing circuit for responding to a plurality of applied-in-parallel analog input signals to produce a serial output signal which is indicative of the simultaneously sampled value of each of said analog input signals, said circuit comprising: (a) sample-and-hold means responsive to sampling enable signals for periodically sampling all of the analog input signals simultaneously and holding each resultant sample value on a sample-and-hold means output channel; (b) first multiplex means comprising a first group of multiplexers each having a plurality of input channels coupled to a mutually exclusive subset of sample-and-hold means output channels and a single multiplexer output channel, each multiplexer of said first group including gating means, which responds to gating signals, for sequentially gating therethrough the resulting signal samples on said subset of sample-and-hold means output channels to said single multiplexer output channel so as to form a first serial signal; (c) second multiplex means having a plurality of input channels each coupled to a different one of said output channels of said first group of multiplexers and including a plurality of gating means, which respond to gating signals, for intermittently and sequentially gating therethrough the plurality of first serial signals from the first group of multiplexers so as to form a second serial signal which comprises a defined sequence of signal samples from said input channels; and (d) timing means for providing said gating signals and said sampling enable signals which are so timed relative to one another that all of said resultant sample values are held until each resultant sample value has been gated through said first and second multiplex means to form said second serial output signal.
Claim 2
Dependent Claim
274 words
A multiplexing circuit for responding to a plurality of applied-in-parallel analog input signals to produce a serial output signal which is indicative of the simultaneously sampled value of each of said analog input signals, said circuit comprising: (a) sample-and-hold means responsive to sampling enable signals for periodically sampling all of the analog input signals simultaneously and holding each resultant sample value on a sample-and-hold means output channel; (b) first multiplex means comprising a first group of multiplexers each having a plurality of input channels coupled to a mutually exclusive subset of sample-and-hold means output channels and a single multiplexer output channel, each multiplexer of said first group including gating means, which responds to gating signals, for sequentially gating therethrough the resulting signal samples on said subset of sample-and-hold means output channels to said single multiplexer output channel so as to form a first serial signal; (c) second multiplex means having a plurality of input channels each coupled to a different one of said output channels of said first group of multiplexers and including a plurality of gating means, which respond to gating signals, for intermittently and sequentially gating therethrough the plurality of first serial signals from the first group of multiplexers so as to form a second serial signal which comprises a defined sequence of signal samples from said input channels; and (d) timing means for providing said gating signals and said sampling enable signals which are so timed relative to one another that all of said resultant sample values are held until each resultant sample value has been gated through said first and second multiplex means to form said second serial output signal.
Claim 3
Dependent Claim
101 words
The multiplexing circuit of claim 1 wherein said sample-and-hold means comprises a plurality of sample-and-hold circuits, one for each of said applied analog input signals, each of said sample-and-hold circuits comprising a switch having an input terminal coupled to receive one of the analog input signals, a capacitor coupled between ground and the output terminal of said switch and an amplifier coupled between the output channel of said sample-and-hold circuit and the output terminal of said switch and wherein the control terminals of said plurality of switches are coupled in parallel to receive said sampling enable signals from said timing means.
Claim 4
Dependent Claim
161 words
A multiplexing circuit for converting a plurality of analog input signals to a single serial signal comprising: (a) sample-and-hold means for simultaneously sampling each of said plurality of analog input signals at defined sample times and for generating a plurality of sample output signals each having a value proportional to the value of the corresponding analog input signal at the most recent sample time; (b) first multiplex means for receiving said plurality of sample output signals and sequentially gating said sampled output signals so as to form at least two gated signals each comprising a series of analog pulses, each pulse being derived from and indicative of one of said parallel analog signals; and (c) second multiplex means for receiving said gated signals from said first multiplex means and for sequentially gating individual analog pulses therefrom to form a serial signal comprising sequences of analog pulses wherein each pulse corresponds to and is indicative of one of said parallel analog signals.
Claim 5
Dependent Claim
161 words
A multiplexing circuit for converting a plurality of analog input signals to a single serial signal comprising: (a) sample-and-hold means for simultaneously sampling each of said plurality of analog input signals at defined sample times and for generating a plurality of sample output signals each having a value proportional to the value of the corresponding analog input signal at the most recent sample time; (b) first multiplex means for receiving said plurality of sample output signals and sequentially gating said sampled output signals so as to form at least two gated signals each comprising a series of analog pulses, each pulse being derived from and indicative of one of said parallel analog signals; and (c) second multiplex means for receiving said gated signals from said first multiplex means and for sequentially gating individual analog pulses therefrom to form a serial signal comprising sequences of analog pulses wherein each pulse corresponds to and is indicative of one of said parallel analog signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |