Electronic multiplexer

Claim 2

An electronic multiplexer comprising: a low-speed multiplexer including a number of input lines from discrete signal sources, and two banks of gates for connecting groups of input lines to respective output lines, a high-speed multiplexer including means for connecting the output lines of the low-speed multiplexer in timed sequence to a single output line, a common switching signal source for said multiplexers including means for applying complementary switching signals of common rate to first and second banks of gates of the low-speed multiplexer to combine signals alternately from the two banks of the low-speed multiplexer, means for applying a switching signal of higher rate to the high-speed multiplexer, means for synchronizing the low-speed and high-speed multiplexers for connecting one of the banks of the low-speed multiplexer during the switching of the second bank of the lowspeed multiplexer, and means at the output of the high-speed multiplexer for disabling the output of the high-speed multiplexer during switching periods.

Claim 3

An electronic time division multiplexer comprising a low-speed multiplexer including two banks of input gates each having a plurality of groups of input lines, means connecting a respective input line from each gate to a common output line, a high-speed multiplexer including a plurality of input lines each connected to a respective output line of the low-speed multiplexer and a number of signal controlling gates for connecting the input lines in timed sequence to a single output line, a clock for developing a basic timing signal for the multiplexer, a counter for deriving a high-speed switching signal for the high-speed multiplexer from the output of said clock, a counter means for deriving a low-speed switching signal for the low-speed multiplexer from the output of the high-speed counter, a synchronizer for comparing the phase of the output of the high-speed counter and low-speed counter and for introducing a correction signal into the input of the low-speed counter means upon the detection of an error in synchronization, a means for applying the high-speed switching signal to the high-speed multiplexer gates to time division multiplex signals arriving at the input lines thereof, a means for applying the low-speed switching signal from the low-speed counter to the gates of the low-speed multiplexer to enable the conduction of incoming signals to the respective output lines, and means at the output of the high-speed multiplexer for disabling the output thereof during the switching intervals of the high-speed multiplexer gates whereby a large number of signals are time division multiplexed on to a single output line with switching transients effectively eliminated from the output signal.

Claim 4

An electronic time division multiplexer comprising a low-speed multiplexer including two banks of input gates each having a plurality of groups of input lines, means connecting a respective input line from each gate to a common output line, a high-speed multiplexer including a plurality of input lines each connected to a respective output line of the low-speed multiplexer and a number of signal controlling gates for connecting the input lines in timed sequence to a single output line, a clock for developing a basic timing signal for the multiplexer, a counter for deriving a high-speed switching signal for the high-speed multiplexer from the output of said clock, a counter means for deriving a low-speed switching signal for the low-speed multiplexer from the output of the high-speed counter, a synchronizer for comparing the phase of the output of the high-speed counter and low-speed counter and for introducing a correction signal into the input of the low-speed counter means upon the detection of an error in synchronization, a means for applying the high-speed switching signal to the high-speed multiplexer gates to time division multiplex signals arriving at the input lines thereof, a means for applying the low-speed switching signal from the low-speed counter to the gates of the low-speed multiplexer to enable the conduction of incoming signals to the respective output lines, and means at the output of the high-speed multiplexer for disabling the output thereof during the switching intervals of the high-speed multiplexer gates whereby a large number of signals are time division multiplexed on to a single output line with switching transients effectively eliminated from the output signal.

Claim 5

The combination in accordance with claim 2 wherein said low-speed counter comprises two counters one for driving each bank of the low-speed multiplexer gates.

Claim 6

The combination in accordance with claim 3 including means for deriving two complementary signals from the output of the high-speed counter and applying the two signals one to each of the two low-speed counters whereby the banks of the low-speed multiplexer gates Are alternately switched from conducting to nonconducting condition.

Claim 7

The combination in accordance with claim 4 wherein the high-speed multiplexer gates comprise a pair of series-shunt connected field effect transistors driven in opposite phase to provide alternate series conduction and shunt blocking when in the conducting condition and series blocking and shunt conduction when in the blocking condition.

Claim 8

A multiplexer, comprising: a first commutator for sequentially connecting a plurality of sets of input lines to a plurality of sets of output lines such that corresponding lines of every input line set in each plurality thereof are connected to the same output line; a second commutator for sequentially connecting the output line sets of said first commutator to a terminal; first means to control said commutators for operation such that said second commutator completes a cycle of operation during each interval in the sequence of operation of said first commutator; second means to control the operation of said first commutator such that the connections made by its sets are made alternately; means to connect the terminal of said second commutator as output for the multiplexer; and means to delay operation of said connecting means until any switching transients in said second commutator are dissipated.

Claim 9

A multiplexer, comprising: a first commutator for sequentially connecting a plurality of sets of input lines to a plurality of sets of output lines such that corresponding lines of every input line set in each plurality thereof are connected to the same output line; a second commutator for sequentially connecting the output line sets of said first commutator to a terminal; first means to control said commutators for operation such that said second commutator completes a cycle of operation during each interval in the sequence of operation of said first commutator; second means to control the operation of said first commutator such that the connections made by its sets are made alternately; means to connect the terminal of said second commutator as output for the multiplexer; and means to delay operation of said connecting means until any switching transients in said second commutator are dissipated.

Claim 10

The combination in accordance with claim 6 wherein said connecting means comprises a gate at the output of said second commutator and driven by said first means.